DMA.CH2.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH2.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH2.TRFCNT=auxDacBufLen;
DMA.CH2.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH3.CTRLB=0x00;//Hi interrupt on block complete
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH2_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=dacBuf_len;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH1[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_ADCA_CH0_gc;//Triggered from ADCA channel 0
DMA.CH0.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH0.SRCADDR0=(((uint16_t)&ADCA.CH0.RESL)>>0)&0xFF;//Source address is ADC
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=auxDacBufLen;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH1.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_ADCA_CH0_gc;//Triggered from ADCA channel 0
DMA.CH0.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH0.SRCADDR0=(((uint16_t)&ADCA.CH0.RESL)>>0)&0xFF;//Source address is ADC
DMA.CH2.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH2.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH2.TRFCNT=auxDacBufLen;
DMA.CH2.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH3.CTRLB=0x00;//Hi interrupt on block complete
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH2_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=dacBuf_len;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH1[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_ADCA_CH0_gc;//Triggered from ADCA channel 0
DMA.CH0.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH0.SRCADDR0=(((uint16_t)&ADCA.CH0.RESL)>>0)&0xFF;//Source address is ADC
DMA.CH1.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH1.TRIGSRC=DMA_CH_TRIGSRC_ADCA_CH0_gc;//Triggered from ADCA channel 0
DMA.CH1.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH1.SRCADDR0=(((uint16_t)&ADCA.CH2.RESL)>>0)&0xFF;//Source address is ADC
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=auxDacBufLen;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH2.CTRLB=0x00;//Hi interrupt on block complete
DMA.CH2.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH2.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH2_gc;//Triggered from TCC0 when it hits PER
DMA.CH2.TRFCNT=dacBuf_len;
DMA.CH2.SRCADDR0=(((uint16_t)&dacBuf_CH1[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_USARTC0_RXC_gc;
DMA.CH0.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH0.SRCADDR0=(((uint16_t)&USARTC0.DATA)>>0)&0xFF;//Source address is ADC
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=auxDacBufLen;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_USARTC0_RXC_gc;
DMA.CH0.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH0.SRCADDR0=(((uint16_t)&USARTC0.DATA)>>0)&0xFF;//Source address is ADC
DMA.CH1.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH1.TRIGSRC=DMA_CH_TRIGSRC_SPIC_gc;
DMA.CH1.TRFCNT=DMA_STANDARD_TRANSFER_LENGTH;
DMA.CH1.SRCADDR0=(((uint16_t)&SPIC.DATA)>>0)&0xFF;//Source address is ADC
DMA.CH2.CTRLB=0x00;//Hi interrupt on block complete
DMA.CH2.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH2.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH2_gc;//Triggered from TCC0 when it hits PER
DMA.CH2.TRFCNT=dacBuf_len;
DMA.CH2.SRCADDR0=(((uint16_t)&dacBuf_CH1[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=auxDacBufLen;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_ADCA_CH0_gc;//Triggered from ADCA channel 0
DMA.CH0.TRFCNT=BUFFER_SIZE;
DMA.CH0.SRCADDR0=(((uint16_t)&ADCA.CH0.RESL)>>0)&0xFF;//Source address is ADC
DMA.CH2.CTRLB=0x00;//Hi interrupt on block complete
DMA.CH2.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH2.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH2_gc;//Triggered from TCC0 when it hits PER
DMA.CH2.TRFCNT=dacBuf_len;
DMA.CH2.SRCADDR0=(((uint16_t)&dacBuf_CH1[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH3.ADDRCTRL=DMA_CH_DESTRELOAD_BURST_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_SRCRELOAD_BLOCK_gc|DMA_CH_SRCDIR_INC_gc;//Dest reloads after each burst, with byte incrementing. Src reloads at end of block, also incrementing address.
DMA.CH3.TRIGSRC=DMA_CH_TRIGSRC_EVSYS_CH1_gc;//Triggered from TCC0 when it hits PER
DMA.CH3.TRFCNT=auxDacBufLen;
DMA.CH3.SRCADDR0=(((uint16_t)&dacBuf_CH2[0])>>0)&0xFF;//Source address is dacbuf
DMA.CH0.CTRLA=DMA_CH_BURSTLEN_2BYTE_gc|DMA_CH_SINGLE_bm|DMA_CH_REPEAT_bm;//Do not repeat!
DMA.CH0.CTRLB=0x00;//No interrupt!
DMA.CH0.ADDRCTRL=DMA_CH_SRCRELOAD_BURST_gc|DMA_CH_SRCDIR_INC_gc|DMA_CH_DESTDIR_INC_gc|DMA_CH_DESTRELOAD_BLOCK_gc;//Source reloads after each burst, with byte incrementing. Dest does not reload, but does increment address.
DMA.CH0.TRIGSRC=DMA_CH_TRIGSRC_ADCA_CH0_gc;//Triggered from ADCA channel 0
DMA.CH0.TRFCNT=BUFFER_SIZE;
DMA.CH0.SRCADDR0=(((uint16_t)&ADCA.CH0.RESL)>>0)&0xFF;//Source address is ADC