Single Endpoint Mode interrupt driven, still single device only

AVR Code/USB_BULK_TEST/src/main.c

@@ -173,6 +173,34 @@ void main_resume_action(void)
 
 void main_sof_action(void)
 {
+	#ifdef SINGLE_ENDPOINT_INTERFACE
+	switch(global_mode){
+		case 0:
+		tiny_dma_loop_mode_0();
+		break;
+		case 1:
+		tiny_dma_loop_mode_1();
+		break;
+		case 2:
+		tiny_dma_loop_mode_2();
+		break;
+		case 3:
+		tiny_dma_loop_mode_3();
+		break;
+		case 4:
+		tiny_dma_loop_mode_4();
+		break;
+		case 6:
+		tiny_dma_loop_mode_6();
+		break;
+		case 7:
+		tiny_dma_loop_mode_7();
+		break;
+		default:
+		break;
+	}
+	#endif
+
 	uds.trfcntL0 = DMA.CH0.TRFCNTL;
 	uds.trfcntH0 = DMA.CH0.TRFCNTH;	
 	uds.trfcntL1 = DMA.CH1.TRFCNTL;
@@ -211,12 +239,17 @@ void main_sof_action(void)
 		currentTrfcnt = DMA.CH0.TRFCNT;
 		debugOnNextEnd = 0;
 	}
-	if(global_mode < 5){
-		usb_state = (DMA.CH0.TRFCNT < 375) ? 1 : 0;
-	}
-	else{
-		usb_state = (DMA.CH0.TRFCNT < 750) ? 1 : 0;
-	}
+	#ifndef SINGLE_ENDPOINT_INTERFACE
+		if(global_mode < 5){
+			usb_state = (DMA.CH0.TRFCNT < 375) ? 1 : 0;
+		}
+		else{
+			usb_state = (DMA.CH0.TRFCNT < 750) ? 1 : 0;
+		}
+	#else
+		usb_state = !usb_state;
+	#endif
+		
 	return;
 }
 
@@ -262,12 +295,6 @@ void iso_callback(udd_ep_status_t status, iram_size_t nb_transfered, udd_ep_id_t
 		}
 		return;
 	#else
-			if (global_mode < 1){
-		udd_ep_run(0x81, false, (uint8_t *)&isoBuf[usb_state * HALFPACKET_SIZE], PACKET_SIZE, iso_callback);
-			}
-			else{
 		udd_ep_run(0x81, false, (uint8_t *)&isoBuf[usb_state * PACKET_SIZE], PACKET_SIZE, iso_callback);
-			}
-
 	#endif
 }

AVR Code/USB_BULK_TEST/src/tiny_dma.c

@@ -87,11 +87,11 @@ void tiny_dma_set_mode_0(void){
 	DMA.CH0.CTRLA = 0x00;
 	DMA.CH0.CTRLA = DMA_CH_RESET_bm;
 		
-	DMA.CH0.CTRLA = DMA_CH_BURSTLEN_1BYTE_gc | DMA_CH_SINGLE_bm | DMA_CH_REPEAT_bm; //Do not repeat!
-	DMA.CH0.CTRLB = 0x00; //No interrupt!
+	DMA.CH0.CTRLA = DMA_CH_BURSTLEN_1BYTE_gc | DMA_CH_SINGLE_bm; //Do not repeat!
+	DMA.CH0.CTRLB = 0x03; //No interrupt!
 	DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_BURST_gc | DMA_CH_SRCDIR_INC_gc | DMA_CH_DESTDIR_INC_gc | DMA_CH_DESTRELOAD_BLOCK_gc;   //Source reloads after each burst, with byte incrementing.  Dest does not reload, but does increment address.
 	DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_ADCA_CH0_gc;	//Triggered from ADCA channel 0
-	DMA.CH0.TRFCNT = PACKET_SIZE;
+	DMA.CH0.TRFCNT = HALFPACKET_SIZE;
 		
 	DMA.CH0.SRCADDR0 = (( (uint16_t) &ADCA.CH0.RESL) >> 0) & 0xFF; //Source address is ADC
 	DMA.CH0.SRCADDR1 = (( (uint16_t) &ADCA.CH0.RESL) >> 8) & 0xFF;
@@ -632,6 +632,15 @@ ISR(DMA_CH0_vect){
 	dma_ch0_ran++;
 	uds.dma_ch0_cntL = dma_ch0_ran & 0xff;
 	uds.dma_ch0_cntH = (dma_ch0_ran >> 8) & 0xff;
+	
+	DMA.CH0.CTRLA = 0x00;	
+	DMA.CH0.CTRLA = DMA_CH_BURSTLEN_1BYTE_gc | DMA_CH_SINGLE_bm; //Do not repeat!
+	DMA.CH0.TRFCNT = HALFPACKET_SIZE;
+			
+	DMA.CH0.DESTADDR0 = (( (uint16_t) &isoBuf[!usb_state * PACKET_SIZE]) >> 0) & 0xFF;  //Dest address is isoBuf
+	DMA.CH0.DESTADDR1 = (( (uint16_t) &isoBuf[!usb_state * PACKET_SIZE]) >> 8) & 0xFF;
+
+	DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm;
 }
 
 ISR(DMA_CH1_vect){