321 lines
7.5 KiB
NASM
321 lines
7.5 KiB
NASM
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;***************************************************************************
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;* Copyright (C) 2006 by Joachim Fritschi, <jfritschi@freenet.de> *
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;* adapted for DiskCryptor by ntldr <ntldr@diskcryptor.net> *
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;* PGP key ID - 0x1B6A24550F33E44A *
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;* *
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;* This program is free software; you can redistribute it and/or modify *
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;* it under the terms of the GNU General Public License as published by *
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;* the Free Software Foundation; either version 2 of the License, or *
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;* (at your option) any later version. *
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;* *
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;* This program is distributed in the hope that it will be useful, *
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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;* GNU General Public License for more details. *
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;* *
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;* You should have received a copy of the GNU General Public License *
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;* along with this program; if not, write to the *
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;* Free Software Foundation, Inc., *
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;* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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;***************************************************************************
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%define a_offset 0
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%define b_offset 4
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%define c_offset 8
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%define d_offset 12
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; Structure of the crypto context struct
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%define s0 0 ; S0 Array 256 Words each
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%define s1 1024 ; S1 Array
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%define s2 2048 ; S2 Array
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%define s3 3072 ; S3 Array
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%define w 4096 ; 8 whitening keys (word)
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%define k 4128 ; key 1-32 ( word )
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; define a few register aliases to allow macro substitution
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%define R0Q rax
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%define R0D eax
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%define R0B al
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%define R0H ah
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%define R1Q rbx
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%define R1D ebx
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%define R1B bl
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%define R1H bh
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%define R2Q rcx
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%define R2D ecx
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%define R2B cl
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%define R2H ch
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%define R3Q rdx
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%define R3D edx
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%define R3B dl
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%define R3H dh
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; performs input whitening
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%macro input_whitening 3
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xor %1, [w+(%2)+%3]
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%endmacro
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; performs input whitening
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%macro output_whitening 3
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xor %1, [w+16+(%2)+%3]
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%endmacro
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; * a input register containing a (rotated 16)
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; * b input register containing b
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; * c input register containing c
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; * d input register containing d (already rol $1)
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; * operations on a and b are interleaved to increase performance
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%macro encrypt_round 5
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movzx edi, %2B
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mov r11d, [r8+rdi*4+s1]
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movzx edi, %1B
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mov r9d, [r8+rdi*4+s2]
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movzx edi, %2H
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ror %2D, 16
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xor r11d, [r8+rdi*4+s2]
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movzx edi, %1H
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ror %1D, 16
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xor r9d, [r8+rdi*4+s3]
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movzx edi, %2B
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xor r11d, [r8+rdi*4+s3]
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movzx edi, %1B
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xor r9d, [r8+rdi*4]
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movzx edi, %2H
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ror %2D, 15
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xor r11d, [r8+rdi*4]
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movzx edi, %1H
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xor r9d, [r8+rdi*4+s1]
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add r9d, r11d
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add r11d, r9d
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add r9d, [r8+k+%5]
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xor %3D, r9d
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rol %3D, 15
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add r11d, [r8+k+4+%5]
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xor %4D, r11d
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%endmacro
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; * a input register containing a(rotated 16)
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; * b input register containing b
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; * c input register containing c
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; * d input register containing d (already rol $1)
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; * operations on a and b are interleaved to increase performance
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; * during the %5 a and b are prepared for the output whitening
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%macro encrypt_last_round 5
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mov r10d, %2D
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shl r10, 32
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movzx edi, %2B
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mov r11d, [r8+rdi*4+s1]
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movzx edi, %1B
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mov r9d, [r8+rdi*4+s2]
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movzx edi, %2H
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ror %2D, 16
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xor r11d, [r8+rdi*4+s2]
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movzx edi, %1H
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ror %1D, 16
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xor r9d, [r8+rdi*4+s3]
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movzx edi, %2B
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xor r11d, [r8+rdi*4+s3]
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movzx edi, %1B
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xor r9d, [r8+rdi*4]
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xor r10, %1Q
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movzx edi, %2H
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xor r11d, [r8+rdi*4]
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movzx edi, %1H
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xor r9d, [r8+rdi*4+s1]
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add r9d, r11d
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add r11d, r9d
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add r9d, [r8+k+%5]
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xor %3D, r9d
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ror %3D, 1
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add r11d, [r8+k+4+%5]
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xor %4D, r11d
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%endmacro
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; * a input register containing a
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; * b input register containing b (rotated 16)
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; * c input register containing c (already rol $1)
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; * d input register containing d
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; * operations on a and b are interleaved to increase performance
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%macro decrypt_round 5
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movzx edi, %1B
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mov r9d, [r8+rdi*4]
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movzx edi, %2B
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mov r11d, [r8+rdi*4+s3]
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movzx edi, %1H
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ror %1D, 16
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xor r9d, [r8+rdi*4+s1]
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movzx edi, %2H
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ror %2D, 16
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xor r11d, [r8+rdi*4]
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movzx edi, %1B
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xor r9d, [r8+rdi*4+s2]
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movzx edi, %2B
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xor r11d, [r8+rdi*4+s1]
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movzx edi, %1H
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ror %1D, 15
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xor r9d, [r8+rdi*4+s3]
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movzx edi, %2H
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xor r11d, [r8+rdi*4+s2]
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add r9d, r11d
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add r11d, r9d
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add r9d, [r8+k+%5]
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xor %3D, r9d
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add r11d, [r8+k+4+%5]
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xor %4D, r11d
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rol %4D, 15
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%endmacro
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; * a input register containing a
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; * b input register containing b
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; * c input register containing c (already rol $1)
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; * d input register containing d
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; * operations on a and b are interleaved to increase performance
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; * during the %5 a and b are prepared for the output whitening
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%macro decrypt_last_round 5
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movzx edi, %1B
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mov r9d, [r8+rdi*4]
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movzx edi, %2B
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mov r11d, [r8+rdi*4+s3]
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movzx edi, %2H
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ror %2D, 16
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xor r11d, [r8+rdi*4]
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movzx edi, %1H
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mov r10d, %2D
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shl r10, 32
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xor r10, %1Q
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ror %1D, 16
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xor r9d, [r8+rdi*4+s1]
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movzx edi, %2B
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xor r11d, [r8+rdi*4+s1]
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movzx edi, %1B
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xor r9d, [r8+rdi*4+s2]
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movzx edi, %2H
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xor r11d, [r8+rdi*4+s2]
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movzx edi, %1H
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xor r9d, [r8+rdi*4+s3]
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add r9d, r11d
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add r11d, r9d
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add r9d, [r8+k+%5]
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xor %3D, r9d
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add r11d, [r8+k+4+%5]
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xor %4D, r11d
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ror %4D, 1
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%endmacro
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global twofish256_encrypt
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global twofish256_decrypt
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align 16
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twofish256_encrypt:
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push R1Q
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push rsi
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push rdi
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; r8 contains the crypto tfm adress
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; rdx contains the output adress
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; rcx contains the input adress
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mov rsi, rdx
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mov R1Q, [rcx]
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mov R3Q, [rcx+8]
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input_whitening R1Q, r8, a_offset
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input_whitening R3Q, r8, c_offset
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mov R0D, R1D
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rol R0D, 16
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shr R1Q, 32
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mov R2D, R3D
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shr R3Q, 32
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rol R3D, 1
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encrypt_round R0,R1,R2,R3,0
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encrypt_round R2,R3,R0,R1,8
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encrypt_round R0,R1,R2,R3,2*8
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encrypt_round R2,R3,R0,R1,3*8
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encrypt_round R0,R1,R2,R3,4*8
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encrypt_round R2,R3,R0,R1,5*8
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encrypt_round R0,R1,R2,R3,6*8
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encrypt_round R2,R3,R0,R1,7*8
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encrypt_round R0,R1,R2,R3,8*8
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encrypt_round R2,R3,R0,R1,9*8
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encrypt_round R0,R1,R2,R3,10*8
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encrypt_round R2,R3,R0,R1,11*8
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encrypt_round R0,R1,R2,R3,12*8
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encrypt_round R2,R3,R0,R1,13*8
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encrypt_round R0,R1,R2,R3,14*8
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encrypt_last_round R2,R3,R0,R1,15*8
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output_whitening r10, r8, a_offset
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mov [rsi], r10
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shl R1Q, 32
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xor R1Q, R0Q
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output_whitening R1Q, r8, c_offset
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mov [rsi+8], R1Q
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pop rdi
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pop rsi
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pop R1Q
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ret
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align 16
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twofish256_decrypt:
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push R1Q
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push rsi
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push rdi
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; r8 contains the crypto tfm adress
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; rdx contains the output adress
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; rcx contains the input adress
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mov rsi, rdx
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mov R1Q, [rcx]
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mov R3Q, [rcx+8]
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output_whitening R1Q, r8, a_offset
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output_whitening R3Q, r8, c_offset
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mov R0D, R1D
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shr R1Q, 32
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rol R1D, 16
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mov R2D, R3D
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shr R3Q, 32
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rol R2D, 1
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decrypt_round R0,R1,R2,R3,15*8
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decrypt_round R2,R3,R0,R1,14*8
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decrypt_round R0,R1,R2,R3,13*8
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decrypt_round R2,R3,R0,R1,12*8
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decrypt_round R0,R1,R2,R3,11*8
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decrypt_round R2,R3,R0,R1,10*8
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decrypt_round R0,R1,R2,R3,9*8
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decrypt_round R2,R3,R0,R1,8*8
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decrypt_round R0,R1,R2,R3,7*8
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decrypt_round R2,R3,R0,R1,6*8
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decrypt_round R0,R1,R2,R3,5*8
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decrypt_round R2,R3,R0,R1,4*8
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decrypt_round R0,R1,R2,R3,3*8
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decrypt_round R2,R3,R0,R1,2*8
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decrypt_round R0,R1,R2,R3,1*8
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decrypt_last_round R2,R3,R0,R1,0
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input_whitening r10, r8, a_offset
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mov [rsi], r10
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shl R1Q, 32
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xor R1Q, R0Q
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input_whitening R1Q, r8, c_offset
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mov [rsi+8], R1Q
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pop rdi
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pop rsi
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pop R1Q
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ret
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