mirror of https://github.com/arendst/Tasmota.git
550 lines
19 KiB
Plaintext
550 lines
19 KiB
Plaintext
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#include <SPI.h>
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/**
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* Copyright (c) 2011 panStamp <contact@panstamp.com>
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*
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* This file is part of the panStamp project.
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*
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* panStamp is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* any later version.
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*
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* panStamp is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with panStamp; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
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* USA
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*
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* Author: Daniel Berenguer
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* Creation date: 03/03/2011
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*/
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#ifndef _CC1101_H
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#define _CC1101_H
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//#include "simplespi.h"
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extern "C" {
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#include <stdint.h>
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#include "ccpacket.h"
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}
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/**
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* Carrier frequencies
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*/
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enum CFREQ
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{
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CFREQ_868 = 0,
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CFREQ_915,
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CFREQ_433,
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CFREQ_918,
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CFREQ_LAST
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};
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/**
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* RF STATES
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*/
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enum RFSTATE
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{
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RFSTATE_IDLE = 0,
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RFSTATE_RX,
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RFSTATE_TX
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};
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/**
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* Frequency channels
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*/
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#define NUMBER_OF_FCHANNELS 10
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/**
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* Type of transfers
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*/
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#define WRITE_BURST 0x40
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#define READ_SINGLE 0x80
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#define READ_BURST 0xC0
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/**
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* Type of register
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*/
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#define CC1101_CONFIG_REGISTER READ_SINGLE
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#define CC1101_STATUS_REGISTER READ_BURST
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/**
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* PATABLE & FIFO's
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*/
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#define CC1101_PATABLE 0x3E // PATABLE address
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#define CC1101_TXFIFO 0x3F // TX FIFO address
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#define CC1101_RXFIFO 0x3F // RX FIFO address
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/**
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* Command strobes
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*/
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#define CC1101_SRES 0x30 // Reset CC1101 chip
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#define CC1101_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
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// Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
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#define CC1101_SXOFF 0x32 // Turn off crystal oscillator
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#define CC1101_SCAL 0x33 // Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without
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// setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
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#define CC1101_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1
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#define CC1101_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
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// If in RX state and CCA is enabled: Only go to TX if channel is clear
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#define CC1101_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable
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#define CC1101_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if
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// WORCTRL.RC_PD=0
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#define CC1101_SPWD 0x39 // Enter power down mode when CSn goes high
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#define CC1101_SFRX 0x3A // Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states
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#define CC1101_SFTX 0x3B // Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states
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#define CC1101_SWORRST 0x3C // Reset real time clock to Event1 value
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#define CC1101_SNOP 0x3D // No operation. May be used to get access to the chip status byte
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/**
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* CC1101 configuration registers
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*/
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#define CC1101_IOCFG2 0x00 // GDO2 Output Pin Configuration
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#define CC1101_IOCFG1 0x01 // GDO1 Output Pin Configuration
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#define CC1101_IOCFG0 0x02 // GDO0 Output Pin Configuration
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#define CC1101_FIFOTHR 0x03 // RX FIFO and TX FIFO Thresholds
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#define CC1101_SYNC1 0x04 // Sync Word, High Byte
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#define CC1101_SYNC0 0x05 // Sync Word, Low Byte
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#define CC1101_PKTLEN 0x06 // Packet Length
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#define CC1101_PKTCTRL1 0x07 // Packet Automation Control
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#define CC1101_PKTCTRL0 0x08 // Packet Automation Control
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#define CC1101_ADDR 0x09 // Device Address
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#define CC1101_CHANNR 0x0A // Channel Number
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#define CC1101_FSCTRL1 0x0B // Frequency Synthesizer Control
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#define CC1101_FSCTRL0 0x0C // Frequency Synthesizer Control
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#define CC1101_FREQ2 0x0D // Frequency Control Word, High Byte
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#define CC1101_FREQ1 0x0E // Frequency Control Word, Middle Byte
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#define CC1101_FREQ0 0x0F // Frequency Control Word, Low Byte
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#define CC1101_MDMCFG4 0x10 // Modem Configuration
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#define CC1101_MDMCFG3 0x11 // Modem Configuration
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#define CC1101_MDMCFG2 0x12 // Modem Configuration
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#define CC1101_MDMCFG1 0x13 // Modem Configuration
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#define CC1101_MDMCFG0 0x14 // Modem Configuration
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#define CC1101_DEVIATN 0x15 // Modem Deviation Setting
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#define CC1101_MCSM2 0x16 // Main Radio Control State Machine Configuration
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#define CC1101_MCSM1 0x17 // Main Radio Control State Machine Configuration
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#define CC1101_MCSM0 0x18 // Main Radio Control State Machine Configuration
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#define CC1101_FOCCFG 0x19 // Frequency Offset Compensation Configuration
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#define CC1101_BSCFG 0x1A // Bit Synchronization Configuration
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#define CC1101_AGCCTRL2 0x1B // AGC Control
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#define CC1101_AGCCTRL1 0x1C // AGC Control
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#define CC1101_AGCCTRL0 0x1D // AGC Control
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#define CC1101_WOREVT1 0x1E // High Byte Event0 Timeout
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#define CC1101_WOREVT0 0x1F // Low Byte Event0 Timeout
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#define CC1101_WORCTRL 0x20 // Wake On Radio Control
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#define CC1101_FREND1 0x21 // Front End RX Configuration
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#define CC1101_FREND0 0x22 // Front End TX Configuration
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#define CC1101_FSCAL3 0x23 // Frequency Synthesizer Calibration
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#define CC1101_FSCAL2 0x24 // Frequency Synthesizer Calibration
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#define CC1101_FSCAL1 0x25 // Frequency Synthesizer Calibration
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#define CC1101_FSCAL0 0x26 // Frequency Synthesizer Calibration
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#define CC1101_RCCTRL1 0x27 // RC Oscillator Configuration
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#define CC1101_RCCTRL0 0x28 // RC Oscillator Configuration
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#define CC1101_FSTEST 0x29 // Frequency Synthesizer Calibration Control
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#define CC1101_PTEST 0x2A // Production Test
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#define CC1101_AGCTEST 0x2B // AGC Test
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#define CC1101_TEST2 0x2C // Various Test Settings
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#define CC1101_TEST1 0x2D // Various Test Settings
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#define CC1101_TEST0 0x2E // Various Test Settings
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/**
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* Status registers
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*/
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#define CC1101_PARTNUM 0x30 // Chip ID
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#define CC1101_VERSION 0x31 // Chip ID
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#define CC1101_FREQEST 0x32 // Frequency Offset Estimate from Demodulator
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#define CC1101_LQI 0x33 // Demodulator Estimate for Link Quality
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#define CC1101_RSSI 0x34 // Received Signal Strength Indication
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#define CC1101_MARCSTATE 0x35 // Main Radio Control State Machine State
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#define CC1101_WORTIME1 0x36 // High Byte of WOR Time
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#define CC1101_WORTIME0 0x37 // Low Byte of WOR Time
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#define CC1101_PKTSTATUS 0x38 // Current GDOx Status and Packet Status
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#define CC1101_VCO_VC_DAC 0x39 // Current Setting from PLL Calibration Module
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#define CC1101_TXBYTES 0x3A // Underflow and Number of Bytes
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#define CC1101_RXBYTES 0x3B // Overflow and Number of Bytes
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#define CC1101_RCCTRL1_STATUS 0x3C // Last RC Oscillator Calibration Result
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#define CC1101_RCCTRL0_STATUS 0x3D // Last RC Oscillator Calibration Result
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/**
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* CC1101 configuration registers - Default values extracted from SmartRF Studio
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*
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* Configuration:
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*
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* Deviation = 20.629883
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* Base frequency = 867.999939
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* Carrier frequency = 867.999939
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* Channel number = 0
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* Carrier frequency = 867.999939
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* Modulated = true
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* Modulation format = GFSK
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* Manchester enable = false
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* Data whitening = off
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* Sync word qualifier mode = 30/32 sync word bits detected
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* Preamble count = 4
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* Channel spacing = 199.951172
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* Carrier frequency = 867.999939
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* Data rate = 38.3835 Kbps
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* RX filter BW = 101.562500
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* Data format = Normal mode
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* Length config = Variable packet length mode. Packet length configured by the first byte after sync word
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* CRC enable = true
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* Packet length = 255
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* Device address = 1
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* Address config = Enable address check
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* Append status = Append two status bytes to the payload of the packet. The status bytes contain RSSI and
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* LQI values, as well as CRC OK
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* CRC autoflush = false
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* PA ramping = false
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* TX power = 12
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* GDO0 mode = Asserts when sync word has been sent / received, and de-asserts at the end of the packet.
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* In RX, the pin will also de-assert when a packet is discarded due to address or maximum length filtering
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* or when the radio enters RXFIFO_OVERFLOW state. In TX the pin will de-assert if the TX FIFO underflows
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* Settings optimized for low current consumption
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*/
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//#define CC1101_DEFVAL_IOCFG2 0x29 // GDO2 Output Pin Configuration
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#define CC1101_DEFVAL_IOCFG2 0x0D // GDO2 Output Pin Configuration
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#define CC1101_DEFVAL_IOCFG1 0x2E // GDO1 Output Pin Configuration
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#define CC1101_DEFVAL_IOCFG0 0x2D // GDO0 Output Pin Configuration
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#define CC1101_DEFVAL_FIFOTHR 0x07 // RX FIFO and TX FIFO Thresholds
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#define CC1101_DEFVAL_SYNC1 0xD3 // Synchronization word, high byte
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#define CC1101_DEFVAL_SYNC0 0x91 // Synchronization word, low byte
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#define CC1101_DEFVAL_PKTLEN 0x3D // Packet Length
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#define CC1101_DEFVAL_PKTCTRL1 0x04 // Packet Automation Control
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#define CC1101_DEFVAL_PKTCTRL0 0x32 // Packet Automation Control
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#define CC1101_DEFVAL_ADDR 0xFF // Device Address
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#define CC1101_DEFVAL_CHANNR 0x00 // Channel Number
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#define CC1101_DEFVAL_FSCTRL1 0x06 // Frequency Synthesizer Control
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#define CC1101_DEFVAL_FSCTRL0 0x00 // Frequency Synthesizer Control
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// Carrier frequency = 868 MHz
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#define CC1101_DEFVAL_FREQ2_868 0x21 // Frequency Control Word, High Byte
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#define CC1101_DEFVAL_FREQ1_868 0x62 // Frequency Control Word, Middle Byte
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#define CC1101_DEFVAL_FREQ0_868 0x76 // Frequency Control Word, Low Byte
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// Carrier frequency = 902 MHz
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#define CC1101_DEFVAL_FREQ2_915 0x22 // Frequency Control Word, High Byte
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#define CC1101_DEFVAL_FREQ1_915 0xB1 // Frequency Control Word, Middle Byte
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#define CC1101_DEFVAL_FREQ0_915 0x3B // Frequency Control Word, Low Byte
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// Carrier frequency = 918 MHz
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#define CC1101_DEFVAL_FREQ2_918 0x23 // Frequency Control Word, High Byte
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#define CC1101_DEFVAL_FREQ1_918 0x4E // Frequency Control Word, Middle Byte
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#define CC1101_DEFVAL_FREQ0_918 0xC4 // Frequency Control Word, Low Byte
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// Carrier frequency = 433 MHz
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#define CC1101_DEFVAL_FREQ2_433 0x10 // Frequency Control Word, High Byte
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#define CC1101_DEFVAL_FREQ1_433 0xB0 // Frequency Control Word, Middle Byte
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#define CC1101_DEFVAL_FREQ0_433 0xB0 // Frequency Control Word, Low Byte
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#define CC1101_DEFVAL_MDMCFG4 0xA9 // Modem Configuration
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#define CC1101_DEFVAL_MDMCFG3 0xE4 // Modem Configuration
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#define CC1101_DEFVAL_MDMCFG2 0x30 // Modem Configuration
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#define CC1101_DEFVAL_MDMCFG1 0x22 // Modem Configuration
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#define CC1101_DEFVAL_MDMCFG0 0xF8 // Modem Configuration
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#define CC1101_DEFVAL_DEVIATN 0x00 // Modem Deviation Setting
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#define CC1101_DEFVAL_MCSM2 0x07 // Main Radio Control State Machine Configuration
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//#define CC1101_DEFVAL_MCSM1 0x30 // Main Radio Control State Machine Configuration
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#define CC1101_DEFVAL_MCSM1 0x30 // Main Radio Control State Machine Configuration
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#define CC1101_DEFVAL_MCSM0 0x18 // Main Radio Control State Machine Configuration
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#define CC1101_DEFVAL_FOCCFG 0x14 // Frequency Offset Compensation Configuration
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#define CC1101_DEFVAL_BSCFG 0x6C // Bit Synchronization Configuration
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#define CC1101_DEFVAL_AGCCTRL2 0x04 // AGC Control
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#define CC1101_DEFVAL_AGCCTRL1 0x00 // AGC Control
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#define CC1101_DEFVAL_AGCCTRL0 0x92 // AGC Control
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#define CC1101_DEFVAL_WOREVT1 0x87 // High Byte Event0 Timeout
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#define CC1101_DEFVAL_WOREVT0 0x6B // Low Byte Event0 Timeout
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#define CC1101_DEFVAL_WORCTRL 0xF8 // Wake On Radio Control
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#define CC1101_DEFVAL_FREND1 0xB6 // Front End RX Configuration
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#define CC1101_DEFVAL_FREND0 0x11 // Front End TX Configuration
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#define CC1101_DEFVAL_FSCAL3 0xE9 // Frequency Synthesizer Calibration
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#define CC1101_DEFVAL_FSCAL2 0x2A // Frequency Synthesizer Calibration
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#define CC1101_DEFVAL_FSCAL1 0x00 // Frequency Synthesizer Calibration
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#define CC1101_DEFVAL_FSCAL0 0x1F // Frequency Synthesizer Calibration
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#define CC1101_DEFVAL_RCCTRL1 0x41 // RC Oscillator Configuration
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#define CC1101_DEFVAL_RCCTRL0 0x00 // RC Oscillator Configuration
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#define CC1101_DEFVAL_FSTEST 0x59 // Frequency Synthesizer Calibration Control
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#define CC1101_DEFVAL_PTEST 0x7F // Production Test
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#define CC1101_DEFVAL_AGCTEST 0x3F // AGC Test
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#define CC1101_DEFVAL_TEST2 0x81 // Various Test Settings
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#define CC1101_DEFVAL_TEST1 0x35 // Various Test Settings
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#define CC1101_DEFVAL_TEST0 0x09 // Various Test Settings
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/**
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* Alias for some default values
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*/
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#define CCDEF_CHANNR CC1101_DEFVAL_CHANNR
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#define CCDEF_SYNC0 CC1101_DEFVAL_SYNC0
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#define CCDEF_SYNC1 CC1101_DEFVAL_SYNC1
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#define CCDEF_ADDR CC1101_DEFVAL_ADDR
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/**
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* Macros
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*/
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// Read CC1101 Config register
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#define readConfigReg(regAddr) readReg(regAddr, CC1101_CONFIG_REGISTER)
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// Read CC1101 Status register
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#define readStatusReg(regAddr) readReg(regAddr, CC1101_STATUS_REGISTER)
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// Enter Rx state
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//#define setRxState() cmdStrobe(CC1101_SRX)
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// Enter Tx state
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//#define setTxState() cmdStrobe(CC1101_STX)
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// Enter IDLE state
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#define setIdleState() cmdStrobe(CC1101_SIDLE)
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// Flush Rx FIFO
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#define flushRxFifo() cmdStrobe(CC1101_SFRX)
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// Flush Tx FIFO
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#define flushTxFifo() cmdStrobe(CC1101_SFTX)
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// Disable address check
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#define disableAddressCheck() writeReg(CC1101_PKTCTRL1, 0x04)
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// Enable address check
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#define enableAddressCheck() writeReg(CC1101_PKTCTRL1, 0x06)
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// Disable CCA
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#define disableCCA() writeReg(CC1101_MCSM1, 0)
|
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// Enable CCA
|
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#define enableCCA() writeReg(CC1101_MCSM1, CC1101_DEFVAL_MCSM1)
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// Set PATABLE single byte
|
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#define setTxPowerAmp(setting) paTableByte = setting
|
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// PATABLE values
|
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#define PA_LowPower 0x60
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#define PA_LongDistance 0xC0
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/**
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* Class: CC1101
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*
|
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* Description:
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* CC1101 interface
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*/
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class CC1101
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{
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private:
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/**
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* Atmega's SPI interface
|
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*/
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SPIClass spi;
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||
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/**
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* writeBurstReg
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*
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* Write multiple registers into the CC1101 IC via SPI
|
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*
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* 'regAddr' Register address
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* 'buffer' Data to be writen
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||
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* 'len' Data length
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||
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*/
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void writeBurstReg(uint8_t regAddr, uint8_t* buffer, uint8_t len);
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/**
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* readBurstReg
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*
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* Read burst data from CC1101 via SPI
|
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*
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||
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* 'buffer' Buffer where to copy the result to
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* 'regAddr' Register address
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||
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* 'len' Data length
|
||
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|
*/
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void readBurstReg(uint8_t * buffer, uint8_t regAddr, uint8_t len);
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|
||
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/**
|
||
|
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* setRegsFromEeprom
|
||
|
|
*
|
||
|
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* Set registers from EEPROM
|
||
|
|
*/
|
||
|
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void setRegsFromEeprom(void);
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||
|
|
|
||
|
|
public:
|
||
|
|
/*
|
||
|
|
* RF state
|
||
|
|
*/
|
||
|
|
uint8_t rfState;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Tx Power byte (single PATABLE config)
|
||
|
|
*/
|
||
|
|
uint8_t paTableByte;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Carrier frequency
|
||
|
|
*/
|
||
|
|
uint8_t carrierFreq;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Frequency channel
|
||
|
|
*/
|
||
|
|
uint8_t channel;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Synchronization word
|
||
|
|
*/
|
||
|
|
uint8_t syncWord[2];
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Device address
|
||
|
|
*/
|
||
|
|
uint8_t devAddress;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* CC1101
|
||
|
|
*
|
||
|
|
* Class constructor
|
||
|
|
*/
|
||
|
|
CC1101(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* cmdStrobe
|
||
|
|
*
|
||
|
|
* Send command strobe to the CC1101 IC via SPI
|
||
|
|
*
|
||
|
|
* 'cmd' Command strobe
|
||
|
|
*/
|
||
|
|
void cmdStrobe(uint8_t cmd);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* wakeUp
|
||
|
|
*
|
||
|
|
* Wake up CC1101 from Power Down state
|
||
|
|
*/
|
||
|
|
void wakeUp(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* readReg
|
||
|
|
*
|
||
|
|
* Read CC1101 register via SPI
|
||
|
|
*
|
||
|
|
* 'regAddr' Register address
|
||
|
|
* 'regType' Type of register: CC1101_CONFIG_REGISTER or CC1101_STATUS_REGISTER
|
||
|
|
*
|
||
|
|
* Return:
|
||
|
|
* Data byte returned by the CC1101 IC
|
||
|
|
*/
|
||
|
|
uint8_t readReg(uint8_t regAddr, uint8_t regType);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* writeReg
|
||
|
|
*
|
||
|
|
* Write single register into the CC1101 IC via SPI
|
||
|
|
*
|
||
|
|
* 'regAddr' Register address
|
||
|
|
* 'value' Value to be writen
|
||
|
|
*/
|
||
|
|
void writeReg(uint8_t regAddr, uint8_t value);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setCCregs
|
||
|
|
*
|
||
|
|
* Configure CC1101 registers
|
||
|
|
*/
|
||
|
|
void setCCregs(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* reset
|
||
|
|
*
|
||
|
|
* Reset CC1101
|
||
|
|
*/
|
||
|
|
void reset(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* init
|
||
|
|
*
|
||
|
|
* Initialize CC1101 radio
|
||
|
|
*
|
||
|
|
* @param freq Carrier frequency
|
||
|
|
*/
|
||
|
|
void init(uint8_t freq=CFREQ_868);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setSyncWord
|
||
|
|
*
|
||
|
|
* Set synchronization word
|
||
|
|
*
|
||
|
|
* 'syncH' Synchronization word - High byte
|
||
|
|
* 'syncL' Synchronization word - Low byte
|
||
|
|
*/
|
||
|
|
void setSyncWord(uint8_t syncH, uint8_t syncL);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setSyncWord (overriding method)
|
||
|
|
*
|
||
|
|
* Set synchronization word
|
||
|
|
*
|
||
|
|
* 'syncH' Synchronization word - pointer to 2-byte array
|
||
|
|
*/
|
||
|
|
void setSyncWord(uint8_t *sync);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setDevAddress
|
||
|
|
*
|
||
|
|
* Set device address
|
||
|
|
*
|
||
|
|
* 'addr' Device address
|
||
|
|
*/
|
||
|
|
void setDevAddress(uint8_t addr);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setCarrierFreq
|
||
|
|
*
|
||
|
|
* Set carrier frequency
|
||
|
|
*
|
||
|
|
* 'freq' New carrier frequency
|
||
|
|
*/
|
||
|
|
void setCarrierFreq(uint8_t freq);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setChannel
|
||
|
|
*
|
||
|
|
* Set frequency channel
|
||
|
|
*
|
||
|
|
* 'chnl' Frequency channel
|
||
|
|
*/
|
||
|
|
void setChannel(uint8_t chnl);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setPowerDownState
|
||
|
|
*
|
||
|
|
* Put CC1101 into power-down state
|
||
|
|
*/
|
||
|
|
void setPowerDownState();
|
||
|
|
|
||
|
|
/**
|
||
|
|
* sendData
|
||
|
|
*
|
||
|
|
* Send data packet via RF
|
||
|
|
*
|
||
|
|
* 'packet' Packet to be transmitted. First byte is the destination address
|
||
|
|
*
|
||
|
|
* Return:
|
||
|
|
* True if the transmission succeeds
|
||
|
|
* False otherwise
|
||
|
|
*/
|
||
|
|
bool sendData(CCPACKET packet);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* receiveData
|
||
|
|
*
|
||
|
|
* Read data packet from RX FIFO
|
||
|
|
*
|
||
|
|
* Return:
|
||
|
|
* Amount of bytes received
|
||
|
|
*/
|
||
|
|
uint8_t receiveData(CCPACKET *packet);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setRxState
|
||
|
|
*
|
||
|
|
* Enter Rx state
|
||
|
|
*/
|
||
|
|
void setRxState(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* setTxState
|
||
|
|
*
|
||
|
|
* Enter Tx state
|
||
|
|
*/
|
||
|
|
void setTxState(void);
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|