2021-07-12 11:32:27 +01:00
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#ifndef _MCP2515_H_
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#define _MCP2515_H_
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2021-07-14 08:40:36 +01:00
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#include <Arduino.h>
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2021-07-12 11:32:27 +01:00
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#include <SPI.h>
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#include "can.h"
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/*
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* Speed 8M
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*/
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#define MCP_8MHz_1000kBPS_CFG1 (0x00)
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#define MCP_8MHz_1000kBPS_CFG2 (0x80)
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#define MCP_8MHz_1000kBPS_CFG3 (0x80)
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#define MCP_8MHz_500kBPS_CFG1 (0x00)
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#define MCP_8MHz_500kBPS_CFG2 (0x90)
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#define MCP_8MHz_500kBPS_CFG3 (0x82)
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#define MCP_8MHz_250kBPS_CFG1 (0x00)
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#define MCP_8MHz_250kBPS_CFG2 (0xB1)
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#define MCP_8MHz_250kBPS_CFG3 (0x85)
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#define MCP_8MHz_200kBPS_CFG1 (0x00)
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#define MCP_8MHz_200kBPS_CFG2 (0xB4)
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#define MCP_8MHz_200kBPS_CFG3 (0x86)
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#define MCP_8MHz_125kBPS_CFG1 (0x01)
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#define MCP_8MHz_125kBPS_CFG2 (0xB1)
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#define MCP_8MHz_125kBPS_CFG3 (0x85)
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#define MCP_8MHz_100kBPS_CFG1 (0x01)
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#define MCP_8MHz_100kBPS_CFG2 (0xB4)
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#define MCP_8MHz_100kBPS_CFG3 (0x86)
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#define MCP_8MHz_80kBPS_CFG1 (0x01)
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#define MCP_8MHz_80kBPS_CFG2 (0xBF)
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#define MCP_8MHz_80kBPS_CFG3 (0x87)
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#define MCP_8MHz_50kBPS_CFG1 (0x03)
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#define MCP_8MHz_50kBPS_CFG2 (0xB4)
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#define MCP_8MHz_50kBPS_CFG3 (0x86)
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#define MCP_8MHz_40kBPS_CFG1 (0x03)
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#define MCP_8MHz_40kBPS_CFG2 (0xBF)
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#define MCP_8MHz_40kBPS_CFG3 (0x87)
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#define MCP_8MHz_33k3BPS_CFG1 (0x47)
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#define MCP_8MHz_33k3BPS_CFG2 (0xE2)
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#define MCP_8MHz_33k3BPS_CFG3 (0x85)
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#define MCP_8MHz_31k25BPS_CFG1 (0x07)
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#define MCP_8MHz_31k25BPS_CFG2 (0xA4)
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#define MCP_8MHz_31k25BPS_CFG3 (0x84)
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#define MCP_8MHz_20kBPS_CFG1 (0x07)
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#define MCP_8MHz_20kBPS_CFG2 (0xBF)
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#define MCP_8MHz_20kBPS_CFG3 (0x87)
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#define MCP_8MHz_10kBPS_CFG1 (0x0F)
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#define MCP_8MHz_10kBPS_CFG2 (0xBF)
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#define MCP_8MHz_10kBPS_CFG3 (0x87)
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#define MCP_8MHz_5kBPS_CFG1 (0x1F)
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#define MCP_8MHz_5kBPS_CFG2 (0xBF)
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#define MCP_8MHz_5kBPS_CFG3 (0x87)
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/*
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* speed 16M
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*/
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#define MCP_16MHz_1000kBPS_CFG1 (0x00)
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#define MCP_16MHz_1000kBPS_CFG2 (0xD0)
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#define MCP_16MHz_1000kBPS_CFG3 (0x82)
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#define MCP_16MHz_500kBPS_CFG1 (0x00)
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#define MCP_16MHz_500kBPS_CFG2 (0xF0)
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#define MCP_16MHz_500kBPS_CFG3 (0x86)
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#define MCP_16MHz_250kBPS_CFG1 (0x41)
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#define MCP_16MHz_250kBPS_CFG2 (0xF1)
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#define MCP_16MHz_250kBPS_CFG3 (0x85)
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#define MCP_16MHz_200kBPS_CFG1 (0x01)
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#define MCP_16MHz_200kBPS_CFG2 (0xFA)
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#define MCP_16MHz_200kBPS_CFG3 (0x87)
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#define MCP_16MHz_125kBPS_CFG1 (0x03)
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#define MCP_16MHz_125kBPS_CFG2 (0xF0)
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#define MCP_16MHz_125kBPS_CFG3 (0x86)
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#define MCP_16MHz_100kBPS_CFG1 (0x03)
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#define MCP_16MHz_100kBPS_CFG2 (0xFA)
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#define MCP_16MHz_100kBPS_CFG3 (0x87)
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#define MCP_16MHz_80kBPS_CFG1 (0x03)
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#define MCP_16MHz_80kBPS_CFG2 (0xFF)
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#define MCP_16MHz_80kBPS_CFG3 (0x87)
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#define MCP_16MHz_50kBPS_CFG1 (0x07)
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#define MCP_16MHz_50kBPS_CFG2 (0xFA)
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#define MCP_16MHz_50kBPS_CFG3 (0x87)
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#define MCP_16MHz_40kBPS_CFG1 (0x07)
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#define MCP_16MHz_40kBPS_CFG2 (0xFF)
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#define MCP_16MHz_40kBPS_CFG3 (0x87)
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#define MCP_16MHz_33k3BPS_CFG1 (0x4E)
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#define MCP_16MHz_33k3BPS_CFG2 (0xF1)
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#define MCP_16MHz_33k3BPS_CFG3 (0x85)
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#define MCP_16MHz_20kBPS_CFG1 (0x0F)
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#define MCP_16MHz_20kBPS_CFG2 (0xFF)
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#define MCP_16MHz_20kBPS_CFG3 (0x87)
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#define MCP_16MHz_10kBPS_CFG1 (0x1F)
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#define MCP_16MHz_10kBPS_CFG2 (0xFF)
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#define MCP_16MHz_10kBPS_CFG3 (0x87)
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#define MCP_16MHz_5kBPS_CFG1 (0x3F)
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#define MCP_16MHz_5kBPS_CFG2 (0xFF)
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#define MCP_16MHz_5kBPS_CFG3 (0x87)
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/*
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* speed 20M
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*/
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#define MCP_20MHz_1000kBPS_CFG1 (0x00)
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#define MCP_20MHz_1000kBPS_CFG2 (0xD9)
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#define MCP_20MHz_1000kBPS_CFG3 (0x82)
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#define MCP_20MHz_500kBPS_CFG1 (0x00)
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#define MCP_20MHz_500kBPS_CFG2 (0xFA)
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#define MCP_20MHz_500kBPS_CFG3 (0x87)
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#define MCP_20MHz_250kBPS_CFG1 (0x41)
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#define MCP_20MHz_250kBPS_CFG2 (0xFB)
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#define MCP_20MHz_250kBPS_CFG3 (0x86)
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#define MCP_20MHz_200kBPS_CFG1 (0x01)
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#define MCP_20MHz_200kBPS_CFG2 (0xFF)
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#define MCP_20MHz_200kBPS_CFG3 (0x87)
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#define MCP_20MHz_125kBPS_CFG1 (0x03)
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#define MCP_20MHz_125kBPS_CFG2 (0xFA)
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#define MCP_20MHz_125kBPS_CFG3 (0x87)
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#define MCP_20MHz_100kBPS_CFG1 (0x04)
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#define MCP_20MHz_100kBPS_CFG2 (0xFA)
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#define MCP_20MHz_100kBPS_CFG3 (0x87)
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#define MCP_20MHz_80kBPS_CFG1 (0x04)
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#define MCP_20MHz_80kBPS_CFG2 (0xFF)
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#define MCP_20MHz_80kBPS_CFG3 (0x87)
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#define MCP_20MHz_50kBPS_CFG1 (0x09)
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#define MCP_20MHz_50kBPS_CFG2 (0xFA)
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#define MCP_20MHz_50kBPS_CFG3 (0x87)
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#define MCP_20MHz_40kBPS_CFG1 (0x09)
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#define MCP_20MHz_40kBPS_CFG2 (0xFF)
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#define MCP_20MHz_40kBPS_CFG3 (0x87)
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enum CAN_CLOCK {
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MCP_20MHZ,
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MCP_16MHZ,
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MCP_8MHZ
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};
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enum CAN_SPEED {
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CAN_5KBPS,
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CAN_10KBPS,
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CAN_20KBPS,
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CAN_31K25BPS,
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CAN_33KBPS,
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CAN_40KBPS,
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CAN_50KBPS,
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CAN_80KBPS,
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CAN_83K3BPS,
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CAN_95KBPS,
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CAN_100KBPS,
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CAN_125KBPS,
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CAN_200KBPS,
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CAN_250KBPS,
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CAN_500KBPS,
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CAN_1000KBPS
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};
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class MCP2515
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{
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public:
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enum ERROR {
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ERROR_OK = 0,
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ERROR_FAIL = 1,
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ERROR_ALLTXBUSY = 2,
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ERROR_FAILINIT = 3,
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ERROR_FAILTX = 4,
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ERROR_NOMSG = 5
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};
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enum MASK {
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MASK0,
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MASK1
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};
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enum RXF {
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RXF0 = 0,
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RXF1 = 1,
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RXF2 = 2,
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RXF3 = 3,
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RXF4 = 4,
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RXF5 = 5
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};
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enum RXBn {
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RXB0 = 0,
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RXB1 = 1
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};
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enum TXBn {
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TXB0 = 0,
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TXB1 = 1,
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TXB2 = 2
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};
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enum /*class*/ CANINTF : uint8_t {
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CANINTF_RX0IF = 0x01,
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CANINTF_RX1IF = 0x02,
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CANINTF_TX0IF = 0x04,
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CANINTF_TX1IF = 0x08,
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CANINTF_TX2IF = 0x10,
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CANINTF_ERRIF = 0x20,
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CANINTF_WAKIF = 0x40,
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CANINTF_MERRF = 0x80
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};
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private:
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static const uint8_t CANCTRL_REQOP = 0xE0;
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static const uint8_t CANCTRL_ABAT = 0x10;
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static const uint8_t CANCTRL_OSM = 0x08;
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static const uint8_t CANCTRL_CLKEN = 0x04;
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static const uint8_t CANCTRL_CLKPRE = 0x03;
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enum /*class*/ CANCTRL_REQOP_MODE : uint8_t {
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CANCTRL_REQOP_NORMAL = 0x00,
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CANCTRL_REQOP_SLEEP = 0x20,
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CANCTRL_REQOP_LOOPBACK = 0x40,
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CANCTRL_REQOP_LISTENONLY = 0x60,
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CANCTRL_REQOP_CONFIG = 0x80,
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CANCTRL_REQOP_POWERUP = 0xE0
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};
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static const uint8_t CANSTAT_OPMOD = 0xE0;
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static const uint8_t CANSTAT_ICOD = 0x0E;
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static const uint8_t TXB_EXIDE_MASK = 0x08;
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static const uint8_t DLC_MASK = 0x0F;
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static const uint8_t RTR_MASK = 0x40;
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static const uint8_t RXBnCTRL_RXM_STD = 0x20;
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static const uint8_t RXBnCTRL_RXM_EXT = 0x40;
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static const uint8_t RXBnCTRL_RXM_STDEXT = 0x00;
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static const uint8_t RXBnCTRL_RXM_MASK = 0x60;
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static const uint8_t RXBnCTRL_RTR = 0x08;
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static const uint8_t RXB0CTRL_BUKT = 0x04;
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static const uint8_t MCP_SIDH = 0;
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static const uint8_t MCP_SIDL = 1;
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static const uint8_t MCP_EID8 = 2;
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static const uint8_t MCP_EID0 = 3;
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static const uint8_t MCP_DLC = 4;
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static const uint8_t MCP_DATA = 5;
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enum /*class*/ STAT : uint8_t {
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STAT_RX0IF = (1<<0),
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STAT_RX1IF = (1<<1)
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};
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static const uint8_t STAT_RXIF_MASK = STAT_RX0IF | STAT_RX1IF;
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enum /*class*/ TXBnCTRL : uint8_t {
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TXB_ABTF = 0x40,
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TXB_MLOA = 0x20,
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TXB_TXERR = 0x10,
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TXB_TXREQ = 0x08,
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TXB_TXIE = 0x04,
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TXB_TXP = 0x03
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};
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enum /*class*/ EFLG : uint8_t {
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EFLG_RX1OVR = (1<<7),
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EFLG_RX0OVR = (1<<6),
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EFLG_TXBO = (1<<5),
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EFLG_TXEP = (1<<4),
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EFLG_RXEP = (1<<3),
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EFLG_TXWAR = (1<<2),
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EFLG_RXWAR = (1<<1),
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EFLG_EWARN = (1<<0)
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};
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static const uint8_t EFLG_ERRORMASK = EFLG_RX1OVR
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| EFLG_RX0OVR
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| EFLG_TXBO
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| EFLG_TXEP
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| EFLG_RXEP;
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enum /*class*/ INSTRUCTION : uint8_t {
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INSTRUCTION_WRITE = 0x02,
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INSTRUCTION_READ = 0x03,
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INSTRUCTION_BITMOD = 0x05,
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INSTRUCTION_LOAD_TX0 = 0x40,
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INSTRUCTION_LOAD_TX1 = 0x42,
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INSTRUCTION_LOAD_TX2 = 0x44,
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INSTRUCTION_RTS_TX0 = 0x81,
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INSTRUCTION_RTS_TX1 = 0x82,
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INSTRUCTION_RTS_TX2 = 0x84,
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INSTRUCTION_RTS_ALL = 0x87,
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INSTRUCTION_READ_RX0 = 0x90,
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INSTRUCTION_READ_RX1 = 0x94,
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INSTRUCTION_READ_STATUS = 0xA0,
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INSTRUCTION_RX_STATUS = 0xB0,
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INSTRUCTION_RESET = 0xC0
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};
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enum /*class*/ REGISTER : uint8_t {
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MCP_RXF0SIDH = 0x00,
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MCP_RXF0SIDL = 0x01,
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MCP_RXF0EID8 = 0x02,
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MCP_RXF0EID0 = 0x03,
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MCP_RXF1SIDH = 0x04,
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MCP_RXF1SIDL = 0x05,
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MCP_RXF1EID8 = 0x06,
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MCP_RXF1EID0 = 0x07,
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MCP_RXF2SIDH = 0x08,
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MCP_RXF2SIDL = 0x09,
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MCP_RXF2EID8 = 0x0A,
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MCP_RXF2EID0 = 0x0B,
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MCP_CANSTAT = 0x0E,
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MCP_CANCTRL = 0x0F,
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MCP_RXF3SIDH = 0x10,
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MCP_RXF3SIDL = 0x11,
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MCP_RXF3EID8 = 0x12,
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MCP_RXF3EID0 = 0x13,
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MCP_RXF4SIDH = 0x14,
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MCP_RXF4SIDL = 0x15,
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MCP_RXF4EID8 = 0x16,
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MCP_RXF4EID0 = 0x17,
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MCP_RXF5SIDH = 0x18,
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MCP_RXF5SIDL = 0x19,
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MCP_RXF5EID8 = 0x1A,
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MCP_RXF5EID0 = 0x1B,
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MCP_TEC = 0x1C,
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MCP_REC = 0x1D,
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MCP_RXM0SIDH = 0x20,
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MCP_RXM0SIDL = 0x21,
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MCP_RXM0EID8 = 0x22,
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MCP_RXM0EID0 = 0x23,
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MCP_RXM1SIDH = 0x24,
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MCP_RXM1SIDL = 0x25,
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MCP_RXM1EID8 = 0x26,
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MCP_RXM1EID0 = 0x27,
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MCP_CNF3 = 0x28,
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MCP_CNF2 = 0x29,
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MCP_CNF1 = 0x2A,
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MCP_CANINTE = 0x2B,
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MCP_CANINTF = 0x2C,
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MCP_EFLG = 0x2D,
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MCP_TXB0CTRL = 0x30,
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MCP_TXB0SIDH = 0x31,
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MCP_TXB0SIDL = 0x32,
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MCP_TXB0EID8 = 0x33,
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MCP_TXB0EID0 = 0x34,
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MCP_TXB0DLC = 0x35,
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MCP_TXB0DATA = 0x36,
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MCP_TXB1CTRL = 0x40,
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MCP_TXB1SIDH = 0x41,
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MCP_TXB1SIDL = 0x42,
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MCP_TXB1EID8 = 0x43,
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MCP_TXB1EID0 = 0x44,
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MCP_TXB1DLC = 0x45,
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MCP_TXB1DATA = 0x46,
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MCP_TXB2CTRL = 0x50,
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MCP_TXB2SIDH = 0x51,
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MCP_TXB2SIDL = 0x52,
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MCP_TXB2EID8 = 0x53,
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MCP_TXB2EID0 = 0x54,
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MCP_TXB2DLC = 0x55,
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MCP_TXB2DATA = 0x56,
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MCP_RXB0CTRL = 0x60,
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MCP_RXB0SIDH = 0x61,
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MCP_RXB0SIDL = 0x62,
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MCP_RXB0EID8 = 0x63,
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MCP_RXB0EID0 = 0x64,
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MCP_RXB0DLC = 0x65,
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MCP_RXB0DATA = 0x66,
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MCP_RXB1CTRL = 0x70,
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MCP_RXB1SIDH = 0x71,
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MCP_RXB1SIDL = 0x72,
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MCP_RXB1EID8 = 0x73,
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MCP_RXB1EID0 = 0x74,
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MCP_RXB1DLC = 0x75,
|
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|
MCP_RXB1DATA = 0x76
|
|
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|
|
};
|
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|
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|
|
static const uint32_t SPI_CLOCK = 10000000; // 10MHz
|
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|
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|
|
static const int N_TXBUFFERS = 3;
|
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|
|
static const int N_RXBUFFERS = 2;
|
|
|
|
|
|
|
|
|
|
static const struct TXBn_REGS {
|
|
|
|
|
REGISTER CTRL;
|
|
|
|
|
REGISTER SIDH;
|
|
|
|
|
REGISTER DATA;
|
|
|
|
|
} TXB[N_TXBUFFERS];
|
|
|
|
|
|
|
|
|
|
static const struct RXBn_REGS {
|
|
|
|
|
REGISTER CTRL;
|
|
|
|
|
REGISTER SIDH;
|
|
|
|
|
REGISTER DATA;
|
|
|
|
|
CANINTF CANINTF_RXnIF;
|
|
|
|
|
} RXB[N_RXBUFFERS];
|
|
|
|
|
|
|
|
|
|
uint8_t SPICS;
|
|
|
|
|
|
|
|
|
|
private:
|
|
|
|
|
|
|
|
|
|
void startSPI();
|
|
|
|
|
void endSPI();
|
|
|
|
|
|
|
|
|
|
ERROR setMode(const CANCTRL_REQOP_MODE mode);
|
|
|
|
|
|
|
|
|
|
uint8_t readRegister(const REGISTER reg);
|
|
|
|
|
void readRegisters(const REGISTER reg, uint8_t values[], const uint8_t n);
|
|
|
|
|
void setRegister(const REGISTER reg, const uint8_t value);
|
|
|
|
|
void setRegisters(const REGISTER reg, const uint8_t values[], const uint8_t n);
|
|
|
|
|
void modifyRegister(const REGISTER reg, const uint8_t mask, const uint8_t data);
|
|
|
|
|
|
|
|
|
|
void prepareId(uint8_t *buffer, const bool ext, const uint32_t id);
|
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
MCP2515(const uint8_t _CS);
|
|
|
|
|
ERROR reset(void);
|
|
|
|
|
ERROR setConfigMode();
|
|
|
|
|
ERROR setListenOnlyMode();
|
|
|
|
|
ERROR setSleepMode();
|
|
|
|
|
ERROR setLoopbackMode();
|
|
|
|
|
ERROR setNormalMode();
|
|
|
|
|
ERROR setBitrate(const CAN_SPEED canSpeed);
|
|
|
|
|
ERROR setBitrate(const CAN_SPEED canSpeed, const CAN_CLOCK canClock);
|
|
|
|
|
ERROR setFilterMask(const MASK num, const bool ext, const uint32_t ulData);
|
|
|
|
|
ERROR setFilter(const RXF num, const bool ext, const uint32_t ulData);
|
|
|
|
|
ERROR sendMessage(const TXBn txbn, const struct can_frame *frame);
|
|
|
|
|
ERROR sendMessage(const struct can_frame *frame);
|
|
|
|
|
ERROR readMessage(const RXBn rxbn, struct can_frame *frame);
|
|
|
|
|
ERROR readMessage(struct can_frame *frame);
|
|
|
|
|
bool checkReceive(void);
|
|
|
|
|
bool checkError(void);
|
|
|
|
|
uint8_t getErrorFlags(void);
|
|
|
|
|
void clearRXnOVRFlags(void);
|
|
|
|
|
uint8_t getInterrupts(void);
|
|
|
|
|
uint8_t getInterruptMask(void);
|
|
|
|
|
void clearInterrupts(void);
|
|
|
|
|
void clearTXInterrupts(void);
|
|
|
|
|
uint8_t getStatus(void);
|
|
|
|
|
void clearRXnOVR(void);
|
|
|
|
|
void clearMERR();
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif
|
