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Add ESP32 devicehardware debug info

This commit is contained in:
Theo Arends 2021-04-19 15:34:49 +02:00
parent 09f5902e0b
commit 6c0861a59a
1 changed files with 19 additions and 10 deletions
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29
tasmota/support_esp.ino
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@ -559,18 +559,20 @@ typedef struct {
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_version = chip_ver & 0x7;
AddLog(LOG_LEVEL_DEBUG, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
switch (pkg_version) {
case 0:
if (single_core) { return F("ESP32-S0WDQ6"); }
else { return F("ESP32-D0WDQ6"); }
if (single_core) { return F("ESP32-S0WDQ6"); } // Max 240MHz, Single core, QFN 6*6
else { return F("ESP32-D0WDQ6"); } // Max 240MHz, Dual core, QFN 6*6
case 1:
if (single_core) { return F("ESP32-S0WD"); }
else { return F("ESP32-D0WD"); }
case 2: return F("ESP32-D2WD");
case 4: return F("ESP32-U4WDH");
if (single_core) { return F("ESP32-S0WD"); } // Max 160MHz, Single core, QFN 5*5, Solo 1
else { return F("ESP32-D0WD"); } // Max 240MHz, Dual core, QFN 5*5
case 2: return F("ESP32-D2WD"); // Max 160MHz, Dual core, QFN 5*5, 2MB embedded flash
case 4: return F("ESP32-U4WDH"); // Max 160MHz, Single core, QFN 5*5, 4MB embedded flash
case 5:
if (rev3) { return F("ESP32-PICO-V3"); }
else { return F("ESP32-PICO-D4"); }
if (rev3) { return F("ESP32-PICO-V3"); } // Max 240MHz, Dual core
else { return F("ESP32-PICO-D4"); } // Max 240MHz, Dual core, 4MB embedded flash
case 6: return F("ESP32-PICO-V3-02");
}
#endif // CONFIG_IDF_TARGET_ESP32
@ -590,10 +592,13 @@ typedef struct {
uint32_t pkg_version = chip_ver & 0x7;
// uint32_t pkg_version = esp_efuse_get_pkg_ver();
AddLog(LOG_LEVEL_DEBUG, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
switch (pkg_version) {
case 0: return F("ESP32-S2");
case 1: return F("ESP32-S2FH16");
case 2: return F("ESP32-S2FH32");
case 1: return F("ESP32-S2FH2"); // Max 240MHz, Single core, 2MB embedded flash
case 2: return F("ESP32-S2FH3"); // Max 240MHz, Single core, 4MB embedded flash
case 3: return F("ESP32-S2FN4R2"); // Max 240MHz, Single core, 4MB embedded flash, 2MB embedded PSRAM
}
#endif // CONFIG_IDF_TARGET_ESP32S2
return F("ESP32-S2");
@ -615,6 +620,8 @@ typedef struct {
uint32_t pkg_version = chip_ver & 0x7;
// uint32_t pkg_version = esp_efuse_get_pkg_ver();
AddLog(LOG_LEVEL_DEBUG, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
switch (pkg_version) {
case 0: return F("ESP32-C3");
}
@ -638,6 +645,8 @@ typedef struct {
uint32_t pkg_version = chip_ver & 0x7;
// uint32_t pkg_version = esp_efuse_get_pkg_ver();
AddLog(LOG_LEVEL_DEBUG, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
switch (pkg_version) {
case 0: return F("ESP32-C6");
}