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Fix unstable ETH on Olimex POE

This commit is contained in:
Stephan Hadinger 2022-08-31 10:09:22 +02:00
parent a427f33839
commit b355231721
1 changed files with 25 additions and 0 deletions
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25
tasmota/tasmota_xdrv_driver/xdrv_82_esp32_ethernet.ino
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@ -154,6 +154,31 @@ void EthernetInit(void) {
int eth_power = Pin(GPIO_ETH_PHY_POWER); int eth_power = Pin(GPIO_ETH_PHY_POWER);
int eth_mdc = Pin(GPIO_ETH_PHY_MDC); int eth_mdc = Pin(GPIO_ETH_PHY_MDC);
int eth_mdio = Pin(GPIO_ETH_PHY_MDIO); int eth_mdio = Pin(GPIO_ETH_PHY_MDIO);
#ifdef ESP32
// fix an disconnection issue after rebooting Olimex POE - this forces a clean state for all GPIO involved in RMII
gpio_reset_pin((gpio_num_t)GPIO_ETH_PHY_POWER);
gpio_reset_pin((gpio_num_t)GPIO_ETH_PHY_MDC);
gpio_reset_pin((gpio_num_t)GPIO_ETH_PHY_MDIO);
gpio_reset_pin(GPIO_NUM_19); // EMAC_TXD0 - hardcoded
gpio_reset_pin(GPIO_NUM_21); // EMAC_TX_EN - hardcoded
gpio_reset_pin(GPIO_NUM_22); // EMAC_TXD1 - hardcoded
gpio_reset_pin(GPIO_NUM_25); // EMAC_RXD0 - hardcoded
gpio_reset_pin(GPIO_NUM_26); // EMAC_RXD1 - hardcoded
gpio_reset_pin(GPIO_NUM_27); // EMAC_RX_CRS_DV - hardcoded
switch (Settings->eth_clk_mode) {
case 0: // ETH_CLOCK_GPIO0_IN
case 1: // ETH_CLOCK_GPIO0_OUT
gpio_reset_pin(GPIO_NUM_0);
break;
case 2: // ETH_CLOCK_GPIO16_OUT
gpio_reset_pin(GPIO_NUM_16);
break;
case 3: // ETH_CLOCK_GPIO17_OUT
gpio_reset_pin(GPIO_NUM_17);
break;
}
delay(1);
#endif
if (!ETH.begin(Settings->eth_address, eth_power, eth_mdc, eth_mdio, (eth_phy_type_t)Settings->eth_type, (eth_clock_mode_t)Settings->eth_clk_mode)) { if (!ETH.begin(Settings->eth_address, eth_power, eth_mdc, eth_mdio, (eth_phy_type_t)Settings->eth_type, (eth_clock_mode_t)Settings->eth_clk_mode)) {
AddLog(LOG_LEVEL_DEBUG, PSTR("ETH: Bad PHY type or init error")); AddLog(LOG_LEVEL_DEBUG, PSTR("ETH: Bad PHY type or init error"));
return; return;