mirror of https://github.com/arendst/Tasmota.git
694 lines
19 KiB
C++
694 lines
19 KiB
C++
#include "mcp2515.h"
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const struct MCP2515::TXBn_REGS MCP2515::TXB[MCP2515::N_TXBUFFERS] = {
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{MCP_TXB0CTRL, MCP_TXB0SIDH, MCP_TXB0DATA},
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{MCP_TXB1CTRL, MCP_TXB1SIDH, MCP_TXB1DATA},
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{MCP_TXB2CTRL, MCP_TXB2SIDH, MCP_TXB2DATA}
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};
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const struct MCP2515::RXBn_REGS MCP2515::RXB[N_RXBUFFERS] = {
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{MCP_RXB0CTRL, MCP_RXB0SIDH, MCP_RXB0DATA, CANINTF_RX0IF},
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{MCP_RXB1CTRL, MCP_RXB1SIDH, MCP_RXB1DATA, CANINTF_RX1IF}
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};
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MCP2515::MCP2515(const uint8_t _CS)
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{
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SPI.begin();
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SPICS = _CS;
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pinMode(SPICS, OUTPUT);
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endSPI();
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}
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void MCP2515::startSPI() {
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SPI.beginTransaction(SPISettings(SPI_CLOCK, MSBFIRST, SPI_MODE0));
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digitalWrite(SPICS, LOW);
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}
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void MCP2515::endSPI() {
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digitalWrite(SPICS, HIGH);
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SPI.endTransaction();
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}
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MCP2515::ERROR MCP2515::reset(void)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_RESET);
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endSPI();
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delay(10);
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uint8_t zeros[14];
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memset(zeros, 0, sizeof(zeros));
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setRegisters(MCP_TXB0CTRL, zeros, 14);
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setRegisters(MCP_TXB1CTRL, zeros, 14);
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setRegisters(MCP_TXB2CTRL, zeros, 14);
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setRegister(MCP_RXB0CTRL, 0);
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setRegister(MCP_RXB1CTRL, 0);
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setRegister(MCP_CANINTE, CANINTF_RX0IF | CANINTF_RX1IF | CANINTF_ERRIF | CANINTF_MERRF);
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modifyRegister(MCP_RXB0CTRL,
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RXBnCTRL_RXM_MASK | RXB0CTRL_BUKT,
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RXBnCTRL_RXM_STDEXT | RXB0CTRL_BUKT);
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modifyRegister(MCP_RXB1CTRL, RXBnCTRL_RXM_MASK, RXBnCTRL_RXM_STDEXT);
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// clear filters and masks
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/*RXF filters[] = {RXF0, RXF1, RXF2, RXF3, RXF4, RXF5};
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for (int i=0; i<6; i++) {
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ERROR result = setFilter(filters[i], true, 0);
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if (result != ERROR_OK) {
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return result;
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}
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}
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MASK masks[] = {MASK0, MASK1};
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for (int i=0; i<2; i++) {
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ERROR result = setFilterMask(masks[i], true, 0);
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if (result != ERROR_OK) {
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return result;
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}
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}*/
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return ERROR_OK;
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}
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uint8_t MCP2515::readRegister(const REGISTER reg)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_READ);
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SPI.transfer(reg);
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uint8_t ret = SPI.transfer(0x00);
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endSPI();
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return ret;
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}
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void MCP2515::readRegisters(const REGISTER reg, uint8_t values[], const uint8_t n)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_READ);
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SPI.transfer(reg);
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// mcp2515 has auto-increment of address-pointer
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for (uint8_t i=0; i<n; i++) {
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values[i] = SPI.transfer(0x00);
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}
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endSPI();
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}
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void MCP2515::setRegister(const REGISTER reg, const uint8_t value)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_WRITE);
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SPI.transfer(reg);
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SPI.transfer(value);
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endSPI();
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}
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void MCP2515::setRegisters(const REGISTER reg, const uint8_t values[], const uint8_t n)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_WRITE);
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SPI.transfer(reg);
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for (uint8_t i=0; i<n; i++) {
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SPI.transfer(values[i]);
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}
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endSPI();
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}
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void MCP2515::modifyRegister(const REGISTER reg, const uint8_t mask, const uint8_t data)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_BITMOD);
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SPI.transfer(reg);
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SPI.transfer(mask);
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SPI.transfer(data);
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endSPI();
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}
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uint8_t MCP2515::getStatus(void)
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{
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startSPI();
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SPI.transfer(INSTRUCTION_READ_STATUS);
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uint8_t i = SPI.transfer(0x00);
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endSPI();
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return i;
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}
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MCP2515::ERROR MCP2515::setConfigMode()
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{
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return setMode(CANCTRL_REQOP_CONFIG);
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}
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MCP2515::ERROR MCP2515::setListenOnlyMode()
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{
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return setMode(CANCTRL_REQOP_LISTENONLY);
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}
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MCP2515::ERROR MCP2515::setSleepMode()
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{
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return setMode(CANCTRL_REQOP_SLEEP);
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}
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MCP2515::ERROR MCP2515::setLoopbackMode()
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{
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return setMode(CANCTRL_REQOP_LOOPBACK);
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}
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MCP2515::ERROR MCP2515::setNormalMode()
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{
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return setMode(CANCTRL_REQOP_NORMAL);
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}
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MCP2515::ERROR MCP2515::setMode(const CANCTRL_REQOP_MODE mode)
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{
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modifyRegister(MCP_CANCTRL, CANCTRL_REQOP, mode);
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unsigned long endTime = millis() + 10;
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bool modeMatch = false;
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while (millis() < endTime) {
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uint8_t newmode = readRegister(MCP_CANSTAT);
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newmode &= CANSTAT_OPMOD;
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modeMatch = newmode == mode;
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if (modeMatch) {
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break;
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}
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}
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return modeMatch ? ERROR_OK : ERROR_FAIL;
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}
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MCP2515::ERROR MCP2515::setBitrate(const CAN_SPEED canSpeed)
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{
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return setBitrate(canSpeed, MCP_16MHZ);
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}
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MCP2515::ERROR MCP2515::setBitrate(const CAN_SPEED canSpeed, CAN_CLOCK canClock)
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{
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ERROR error = setConfigMode();
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if (error != ERROR_OK) {
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return error;
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}
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uint8_t set, cfg1, cfg2, cfg3;
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set = 1;
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switch (canClock)
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{
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case (MCP_8MHZ):
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switch (canSpeed)
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{
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case (CAN_5KBPS): // 5KBPS
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cfg1 = MCP_8MHz_5kBPS_CFG1;
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cfg2 = MCP_8MHz_5kBPS_CFG2;
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cfg3 = MCP_8MHz_5kBPS_CFG3;
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break;
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case (CAN_10KBPS): // 10KBPS
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cfg1 = MCP_8MHz_10kBPS_CFG1;
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cfg2 = MCP_8MHz_10kBPS_CFG2;
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cfg3 = MCP_8MHz_10kBPS_CFG3;
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break;
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case (CAN_20KBPS): // 20KBPS
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cfg1 = MCP_8MHz_20kBPS_CFG1;
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cfg2 = MCP_8MHz_20kBPS_CFG2;
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cfg3 = MCP_8MHz_20kBPS_CFG3;
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break;
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case (CAN_31K25BPS): // 31.25KBPS
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cfg1 = MCP_8MHz_31k25BPS_CFG1;
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cfg2 = MCP_8MHz_31k25BPS_CFG2;
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cfg3 = MCP_8MHz_31k25BPS_CFG3;
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break;
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case (CAN_33KBPS): // 33.33KBPS
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cfg1 = MCP_8MHz_33k3BPS_CFG1;
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cfg2 = MCP_8MHz_33k3BPS_CFG2;
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cfg3 = MCP_8MHz_33k3BPS_CFG3;
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break;
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case (CAN_40KBPS): // 40Kbps
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cfg1 = MCP_8MHz_40kBPS_CFG1;
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cfg2 = MCP_8MHz_40kBPS_CFG2;
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cfg3 = MCP_8MHz_40kBPS_CFG3;
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break;
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case (CAN_50KBPS): // 50Kbps
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cfg1 = MCP_8MHz_50kBPS_CFG1;
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cfg2 = MCP_8MHz_50kBPS_CFG2;
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cfg3 = MCP_8MHz_50kBPS_CFG3;
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break;
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case (CAN_80KBPS): // 80Kbps
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cfg1 = MCP_8MHz_80kBPS_CFG1;
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cfg2 = MCP_8MHz_80kBPS_CFG2;
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cfg3 = MCP_8MHz_80kBPS_CFG3;
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break;
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case (CAN_100KBPS): // 100Kbps
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cfg1 = MCP_8MHz_100kBPS_CFG1;
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cfg2 = MCP_8MHz_100kBPS_CFG2;
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cfg3 = MCP_8MHz_100kBPS_CFG3;
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break;
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case (CAN_125KBPS): // 125Kbps
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cfg1 = MCP_8MHz_125kBPS_CFG1;
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cfg2 = MCP_8MHz_125kBPS_CFG2;
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cfg3 = MCP_8MHz_125kBPS_CFG3;
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break;
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case (CAN_200KBPS): // 200Kbps
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cfg1 = MCP_8MHz_200kBPS_CFG1;
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cfg2 = MCP_8MHz_200kBPS_CFG2;
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cfg3 = MCP_8MHz_200kBPS_CFG3;
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break;
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case (CAN_250KBPS): // 250Kbps
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cfg1 = MCP_8MHz_250kBPS_CFG1;
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cfg2 = MCP_8MHz_250kBPS_CFG2;
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cfg3 = MCP_8MHz_250kBPS_CFG3;
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break;
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case (CAN_500KBPS): // 500Kbps
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cfg1 = MCP_8MHz_500kBPS_CFG1;
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cfg2 = MCP_8MHz_500kBPS_CFG2;
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cfg3 = MCP_8MHz_500kBPS_CFG3;
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break;
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case (CAN_1000KBPS): // 1Mbps
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cfg1 = MCP_8MHz_1000kBPS_CFG1;
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cfg2 = MCP_8MHz_1000kBPS_CFG2;
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cfg3 = MCP_8MHz_1000kBPS_CFG3;
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break;
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default:
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set = 0;
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break;
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}
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break;
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case (MCP_16MHZ):
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switch (canSpeed)
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{
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case (CAN_5KBPS): // 5Kbps
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cfg1 = MCP_16MHz_5kBPS_CFG1;
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cfg2 = MCP_16MHz_5kBPS_CFG2;
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cfg3 = MCP_16MHz_5kBPS_CFG3;
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break;
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case (CAN_10KBPS): // 10Kbps
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cfg1 = MCP_16MHz_10kBPS_CFG1;
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cfg2 = MCP_16MHz_10kBPS_CFG2;
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cfg3 = MCP_16MHz_10kBPS_CFG3;
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break;
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case (CAN_20KBPS): // 20Kbps
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cfg1 = MCP_16MHz_20kBPS_CFG1;
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cfg2 = MCP_16MHz_20kBPS_CFG2;
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cfg3 = MCP_16MHz_20kBPS_CFG3;
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break;
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case (CAN_33KBPS): // 20Kbps
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cfg1 = MCP_16MHz_33k3BPS_CFG1;
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cfg2 = MCP_16MHz_33k3BPS_CFG2;
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cfg3 = MCP_16MHz_33k3BPS_CFG3;
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break;
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case (CAN_40KBPS): // 40Kbps
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cfg1 = MCP_16MHz_40kBPS_CFG1;
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cfg2 = MCP_16MHz_40kBPS_CFG2;
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cfg3 = MCP_16MHz_40kBPS_CFG3;
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break;
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case (CAN_50KBPS): // 50Kbps
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cfg2 = MCP_16MHz_50kBPS_CFG2;
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cfg3 = MCP_16MHz_50kBPS_CFG3;
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break;
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case (CAN_80KBPS): // 80Kbps
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cfg1 = MCP_16MHz_80kBPS_CFG1;
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cfg2 = MCP_16MHz_80kBPS_CFG2;
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cfg3 = MCP_16MHz_80kBPS_CFG3;
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break;
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case (CAN_100KBPS): // 100Kbps
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cfg1 = MCP_16MHz_100kBPS_CFG1;
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cfg2 = MCP_16MHz_100kBPS_CFG2;
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cfg3 = MCP_16MHz_100kBPS_CFG3;
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break;
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case (CAN_125KBPS): // 125Kbps
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cfg1 = MCP_16MHz_125kBPS_CFG1;
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cfg2 = MCP_16MHz_125kBPS_CFG2;
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cfg3 = MCP_16MHz_125kBPS_CFG3;
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break;
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case (CAN_200KBPS): // 200Kbps
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cfg1 = MCP_16MHz_200kBPS_CFG1;
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cfg2 = MCP_16MHz_200kBPS_CFG2;
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cfg3 = MCP_16MHz_200kBPS_CFG3;
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break;
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case (CAN_250KBPS): // 250Kbps
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cfg1 = MCP_16MHz_250kBPS_CFG1;
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cfg2 = MCP_16MHz_250kBPS_CFG2;
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cfg3 = MCP_16MHz_250kBPS_CFG3;
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break;
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case (CAN_500KBPS): // 500Kbps
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cfg1 = MCP_16MHz_500kBPS_CFG1;
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cfg2 = MCP_16MHz_500kBPS_CFG2;
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cfg3 = MCP_16MHz_500kBPS_CFG3;
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break;
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case (CAN_1000KBPS): // 1Mbps
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cfg1 = MCP_16MHz_1000kBPS_CFG1;
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cfg2 = MCP_16MHz_1000kBPS_CFG2;
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cfg3 = MCP_16MHz_1000kBPS_CFG3;
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break;
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default:
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set = 0;
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break;
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}
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break;
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case (MCP_20MHZ):
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switch (canSpeed)
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{
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case (CAN_40KBPS): // 40Kbps
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cfg1 = MCP_20MHz_40kBPS_CFG1;
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cfg2 = MCP_20MHz_40kBPS_CFG2;
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cfg3 = MCP_20MHz_40kBPS_CFG3;
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break;
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case (CAN_50KBPS): // 50Kbps
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cfg1 = MCP_20MHz_50kBPS_CFG1;
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cfg2 = MCP_20MHz_50kBPS_CFG2;
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cfg3 = MCP_20MHz_50kBPS_CFG3;
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break;
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case (CAN_80KBPS): // 80Kbps
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cfg1 = MCP_20MHz_80kBPS_CFG1;
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cfg2 = MCP_20MHz_80kBPS_CFG2;
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cfg3 = MCP_20MHz_80kBPS_CFG3;
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break;
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case (CAN_100KBPS): // 100Kbps
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cfg1 = MCP_20MHz_100kBPS_CFG1;
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cfg2 = MCP_20MHz_100kBPS_CFG2;
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cfg3 = MCP_20MHz_100kBPS_CFG3;
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break;
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case (CAN_125KBPS): // 125Kbps
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cfg1 = MCP_20MHz_125kBPS_CFG1;
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cfg2 = MCP_20MHz_125kBPS_CFG2;
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cfg3 = MCP_20MHz_125kBPS_CFG3;
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break;
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case (CAN_200KBPS): // 200Kbps
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cfg1 = MCP_20MHz_200kBPS_CFG1;
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cfg2 = MCP_20MHz_200kBPS_CFG2;
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cfg3 = MCP_20MHz_200kBPS_CFG3;
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break;
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case (CAN_250KBPS): // 250Kbps
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cfg1 = MCP_20MHz_250kBPS_CFG1;
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cfg2 = MCP_20MHz_250kBPS_CFG2;
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cfg3 = MCP_20MHz_250kBPS_CFG3;
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break;
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case (CAN_500KBPS): // 500Kbps
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cfg1 = MCP_20MHz_500kBPS_CFG1;
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cfg2 = MCP_20MHz_500kBPS_CFG2;
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cfg3 = MCP_20MHz_500kBPS_CFG3;
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break;
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case (CAN_1000KBPS): // 1Mbps
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cfg1 = MCP_20MHz_1000kBPS_CFG1;
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cfg2 = MCP_20MHz_1000kBPS_CFG2;
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cfg3 = MCP_20MHz_1000kBPS_CFG3;
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break;
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default:
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set = 0;
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break;
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}
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break;
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default:
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set = 0;
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break;
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}
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if (set) {
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setRegister(MCP_CNF1, cfg1);
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setRegister(MCP_CNF2, cfg2);
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setRegister(MCP_CNF3, cfg3);
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return ERROR_OK;
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}
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else {
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return ERROR_FAIL;
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}
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}
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void MCP2515::prepareId(uint8_t *buffer, const bool ext, const uint32_t id)
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{
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uint16_t canid = (uint16_t)(id & 0x0FFFF);
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if (ext) {
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buffer[MCP_EID0] = (uint8_t) (canid & 0xFF);
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buffer[MCP_EID8] = (uint8_t) (canid >> 8);
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canid = (uint16_t)(id >> 16);
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buffer[MCP_SIDL] = (uint8_t) (canid & 0x03);
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buffer[MCP_SIDL] += (uint8_t) ((canid & 0x1C) << 3);
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buffer[MCP_SIDL] |= TXB_EXIDE_MASK;
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buffer[MCP_SIDH] = (uint8_t) (canid >> 5);
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} else {
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buffer[MCP_SIDH] = (uint8_t) (canid >> 3);
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buffer[MCP_SIDL] = (uint8_t) ((canid & 0x07 ) << 5);
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buffer[MCP_EID0] = 0;
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buffer[MCP_EID8] = 0;
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}
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}
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MCP2515::ERROR MCP2515::setFilterMask(const MASK mask, const bool ext, const uint32_t ulData)
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{
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ERROR res = setConfigMode();
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if (res != ERROR_OK) {
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return res;
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}
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uint8_t tbufdata[4];
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prepareId(tbufdata, ext, ulData);
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REGISTER reg;
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switch (mask) {
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case MASK0: reg = MCP_RXM0SIDH; break;
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case MASK1: reg = MCP_RXM1SIDH; break;
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default:
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return ERROR_FAIL;
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}
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setRegisters(reg, tbufdata, 4);
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return ERROR_OK;
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}
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MCP2515::ERROR MCP2515::setFilter(const RXF num, const bool ext, const uint32_t ulData)
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{
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ERROR res = setConfigMode();
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if (res != ERROR_OK) {
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return res;
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}
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|
|
REGISTER reg;
|
|
|
|
switch (num) {
|
|
case RXF0: reg = MCP_RXF0SIDH; break;
|
|
case RXF1: reg = MCP_RXF1SIDH; break;
|
|
case RXF2: reg = MCP_RXF2SIDH; break;
|
|
case RXF3: reg = MCP_RXF3SIDH; break;
|
|
case RXF4: reg = MCP_RXF4SIDH; break;
|
|
case RXF5: reg = MCP_RXF5SIDH; break;
|
|
default:
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
uint8_t tbufdata[4];
|
|
prepareId(tbufdata, ext, ulData);
|
|
setRegisters(reg, tbufdata, 4);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
MCP2515::ERROR MCP2515::sendMessage(const TXBn txbn, const struct can_frame *frame)
|
|
{
|
|
const struct TXBn_REGS *txbuf = &TXB[txbn];
|
|
|
|
uint8_t data[13];
|
|
|
|
bool ext = (frame->can_id & CAN_EFF_FLAG);
|
|
bool rtr = (frame->can_id & CAN_RTR_FLAG);
|
|
uint32_t id = (frame->can_id & (ext ? CAN_EFF_MASK : CAN_SFF_MASK));
|
|
|
|
prepareId(data, ext, id);
|
|
|
|
data[MCP_DLC] = rtr ? (frame->can_dlc | RTR_MASK) : frame->can_dlc;
|
|
|
|
memcpy(&data[MCP_DATA], frame->data, frame->can_dlc);
|
|
|
|
setRegisters(txbuf->SIDH, data, 5 + frame->can_dlc);
|
|
|
|
modifyRegister(txbuf->CTRL, TXB_TXREQ, TXB_TXREQ);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
MCP2515::ERROR MCP2515::sendMessage(const struct can_frame *frame)
|
|
{
|
|
if (frame->can_dlc > CAN_MAX_DLEN) {
|
|
return ERROR_FAILTX;
|
|
}
|
|
|
|
TXBn txBuffers[N_TXBUFFERS] = {TXB0, TXB1, TXB2};
|
|
|
|
for (int i=0; i<N_TXBUFFERS; i++) {
|
|
const struct TXBn_REGS *txbuf = &TXB[txBuffers[i]];
|
|
uint8_t ctrlval = readRegister(txbuf->CTRL);
|
|
if ( (ctrlval & TXB_TXREQ) == 0 ) {
|
|
return sendMessage(txBuffers[i], frame);
|
|
}
|
|
}
|
|
|
|
return ERROR_FAILTX;
|
|
}
|
|
|
|
MCP2515::ERROR MCP2515::readMessage(const RXBn rxbn, struct can_frame *frame)
|
|
{
|
|
const struct RXBn_REGS *rxb = &RXB[rxbn];
|
|
|
|
uint8_t tbufdata[5];
|
|
|
|
readRegisters(rxb->SIDH, tbufdata, 5);
|
|
|
|
uint32_t id = (tbufdata[MCP_SIDH]<<3) + (tbufdata[MCP_SIDL]>>5);
|
|
|
|
if ( (tbufdata[MCP_SIDL] & TXB_EXIDE_MASK) == TXB_EXIDE_MASK ) {
|
|
id = (id<<2) + (tbufdata[MCP_SIDL] & 0x03);
|
|
id = (id<<8) + tbufdata[MCP_EID8];
|
|
id = (id<<8) + tbufdata[MCP_EID0];
|
|
id |= CAN_EFF_FLAG;
|
|
}
|
|
|
|
uint8_t dlc = (tbufdata[MCP_DLC] & DLC_MASK);
|
|
if (dlc > CAN_MAX_DLEN) {
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
uint8_t ctrl = readRegister(rxb->CTRL);
|
|
if (ctrl & RXBnCTRL_RTR) {
|
|
id |= CAN_RTR_FLAG;
|
|
}
|
|
|
|
frame->can_id = id;
|
|
frame->can_dlc = dlc;
|
|
|
|
readRegisters(rxb->DATA, frame->data, dlc);
|
|
|
|
modifyRegister(MCP_CANINTF, rxb->CANINTF_RXnIF, 0);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
MCP2515::ERROR MCP2515::readMessage(struct can_frame *frame)
|
|
{
|
|
ERROR rc;
|
|
uint8_t stat = getStatus();
|
|
|
|
if ( stat & STAT_RX0IF ) {
|
|
rc = readMessage(RXB0, frame);
|
|
} else if ( stat & STAT_RX1IF ) {
|
|
rc = readMessage(RXB1, frame);
|
|
} else {
|
|
rc = ERROR_NOMSG;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
bool MCP2515::checkReceive(void)
|
|
{
|
|
uint8_t res = getStatus();
|
|
if ( res & STAT_RXIF_MASK ) {
|
|
return true;
|
|
} else {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool MCP2515::checkError(void)
|
|
{
|
|
uint8_t eflg = getErrorFlags();
|
|
|
|
if ( eflg & EFLG_ERRORMASK ) {
|
|
return true;
|
|
} else {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
uint8_t MCP2515::getErrorFlags(void)
|
|
{
|
|
return readRegister(MCP_EFLG);
|
|
}
|
|
|
|
void MCP2515::clearRXnOVRFlags(void)
|
|
{
|
|
modifyRegister(MCP_EFLG, EFLG_RX0OVR | EFLG_RX1OVR, 0);
|
|
}
|
|
|
|
uint8_t MCP2515::getInterrupts(void)
|
|
{
|
|
return readRegister(MCP_CANINTF);
|
|
}
|
|
|
|
void MCP2515::clearInterrupts(void)
|
|
{
|
|
setRegister(MCP_CANINTF, 0);
|
|
}
|
|
|
|
uint8_t MCP2515::getInterruptMask(void)
|
|
{
|
|
return readRegister(MCP_CANINTE);
|
|
}
|
|
|
|
void MCP2515::clearTXInterrupts(void)
|
|
{
|
|
modifyRegister(MCP_CANINTF, (CANINTF_TX0IF | CANINTF_TX1IF | CANINTF_TX2IF), 0);
|
|
}
|
|
|
|
void MCP2515::clearRXnOVR(void)
|
|
{
|
|
uint8_t eflg = getErrorFlags();
|
|
if (eflg != 0) {
|
|
clearRXnOVRFlags();
|
|
clearInterrupts();
|
|
//modifyRegister(MCP_CANINTF, CANINTF_ERRIF, 0);
|
|
}
|
|
|
|
}
|
|
|
|
void MCP2515::clearMERR()
|
|
{
|
|
//modifyRegister(MCP_EFLG, EFLG_RX0OVR | EFLG_RX1OVR, 0);
|
|
//clearInterrupts();
|
|
modifyRegister(MCP_CANINTF, CANINTF_MERRF, 0);
|
|
}
|