260 lines
6.0 KiB
Forth
260 lines
6.0 KiB
Forth
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here constant CAPTURE-START
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[
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: fake ( a - u )
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dup 0= ] here [ and or ;
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]
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:m :: ( - )
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[ >in @ label >in !
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create ] here [ , hide
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does> @ ] m;
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\ jump if bit is 0 or 1 ( addr bit )
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:m j1 ( addr bit ) [ swap fake swap ] 0=until. m;
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:m j0 ( addr bit ) [ swap fake swap ] until. m;
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:m j ( addr ) fake again m;
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:m tx SBUF0 (#!) clra TMR3H (#!) m;
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:m SDA0 ( a ) SDA j0 m;
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:m SDA1 ( a ) SDA j1 m;
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fwd L00.0
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fwd L00.1
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fwd L00.2
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fwd H00.0
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fwd H00.1
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fwd H00.2
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fwd HS
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fwd HP
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fwd LP
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fwd LS
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:m escape RI0 if. RI0 clr ; then m;
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:: L11 begin LS SDA0 SCL 0=until.
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:: Lidle begin begin SDA until. SCL until.
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L11 j
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:: L10.0 3 .t set
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begin L00.0 SDA0 SCL until. begin LS SDA0 SCL 0=until. 2 .t set
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:: L10.1 begin L00.1 SDA0 SCL until. begin LS SDA0 SCL 0=until. 1 .t set
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:: L10.2 begin L00.2 SDA0 SCL until. begin LS SDA0 SCL 0=until. 0 .t set
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tx
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:: H10.0 7 .t set
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:: klak begin H00.0 SDA0 SCL until. begin HS SDA0 SCL 0=until. 6 .t set
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:: H10.1 begin H00.1 SDA0 SCL until. begin HS SDA0 SCL 0=until. 5 .t set
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:: H10.2 begin H00.2 SDA0 SCL until. begin HS SDA0 SCL 0=until. 4 .t set
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L10.0 j
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:: LS $f0 # and $01 # ior tx ( start )
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:: LS2 begin HP SDA1 SCL 0=until.
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H00.0 j
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:: HS $10 (#) ( start )
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:: HS2 begin LP SDA1 SCL 0=until.
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:: L00.0 3 .t set
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begin L10.0 SDA1 SCL until. begin LP SDA1 SCL 0=until.
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:: L00.1 begin L10.1 SDA1 SCL until. begin LP SDA1 SCL 0=until.
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:: L00.2 begin L10.2 SDA1 SCL until. begin LP SDA1 SCL 0=until.
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tx
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:: H00.0 7 .t set
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begin H10.0 SDA1 SCL until. begin HP SDA1 SCL 0=until.
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:: H00.1 begin H10.1 SDA1 SCL until. begin HP SDA1 SCL 0=until.
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:: H00.2 begin H10.2 SDA1 SCL until. begin HP SDA1 SCL 0=until.
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L00.0 j
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:: HP $20 (#)
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\ L11 j
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begin SDA 0=until.
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escape
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HS2 j
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: (warm)
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:: H11 begin HS SDA0 SCL 0=until.
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:: Hidle begin begin SDA until. SCL until.
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H11 j
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:: LP $f0 # and $02 # ior tx
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\ H11 j
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begin SDA 0=until.
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escape
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LS2 j
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: /timer3
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$80 # EIE1 ior! \ Timer 3 interrupt enable
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;
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: timer3\
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$80 ~# EIE1 and! \ Timer 3 interrupt disable
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;
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:m timer3
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SBUF0 (#!) clra
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$7f # TMR3CN and!
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RI0 if.
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RI0 clr
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[ sp dec ]
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[ sp dec ]
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then
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[ reti ] m;
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: capture
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[ IE push ]
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[ ET2 clr ] \ Timer 2 interrupt disable
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[ ES0 clr ] \ UART interrupt disable
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\i2chw
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[ clra ]
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[ FL1 set ] t3+
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(warm)
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t3- [ FL1 clr ]
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/i2chw
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[ IE pop ]
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;
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\ This code all runs in register bank 1:
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\ 0 scratch for heatmap
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\ 1 log
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\ 2
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\ 3 prev cmd
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\ 4 constant 72, for heatmap
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\ 5
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\ 6
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\ 7 caller acc save
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\
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\ FL0 set means this is an address byte
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fwd M00.0
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fwd M10.0
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fwd M10.1
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fwd M10.2
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fwd M10.3
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fwd M10.4
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fwd M10.5
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fwd M10.6
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fwd M10.7
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fwd M10.8
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fwd Mt
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fwd MP
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:m (l!) $f3 , m;
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:m (log!)
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$f3 , a+ m;
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:m wrap
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$7f # 9 and! m;
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:m heat
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\ byte is in t
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FL0 if.
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setc 2/'
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0 (#!)
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4 (#@) $f2 ,
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then
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m;
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:m escape
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7 (#@)
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[
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dirty set
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PSW pop
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reti
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]
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m;
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:: MP
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$00 (#) (log!)
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$01 (#) (log!)
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wrap
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escape
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begin SDA 0=until.
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: (mismatch)
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:: Mt
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begin MP SDA1 SCL 0=until.
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$82 # 3 #! FL0 set
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M00.0 j
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:: M00.6 begin M10.6 SDA1 SCL until. begin MP SDA1 SCL 0=until.
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:: M00.7 begin M10.7 SDA1 SCL until. begin MP SDA1 SCL 0=until. (l!)
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:: M00.8 begin M10.8 SDA1 SCL until. begin MP SDA1 SCL 0=until. heat
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a+ 3 (#@) (l!) a+ wrap
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$83 # 3 #! FL0 clr
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M00.0 j
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:: M10.6 begin M00.6 SDA0 SCL until. begin Mt SDA0 SCL 0=until. 1 .t set
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:: M10.7 begin M00.7 SDA0 SCL until. begin Mt SDA0 SCL 0=until. 1+ (l!)
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:: M10.8 begin M00.8 SDA0 SCL until. begin Mt SDA0 SCL 0=until.
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a+ 3 (#@) $7f # and (l!) a+ wrap
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$83 # 3 #! FL0 clr
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M10.0 j
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:: MP3 MP j
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:: Mt3 Mt j
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:: M00.3 begin M10.3 SDA1 SCL until. begin MP3 SDA1 SCL 0=until.
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:: M00.4 begin M10.4 SDA1 SCL until. begin MP3 SDA1 SCL 0=until.
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:: M00.5 begin M10.5 SDA1 SCL until. begin MP3 SDA1 SCL 0=until.
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M00.6 j
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:: M10.3 begin M00.3 SDA0 SCL until. begin Mt3 SDA0 SCL 0=until. 4 .t set
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:: M10.4 begin M00.4 SDA0 SCL until. begin Mt3 SDA0 SCL 0=until. 3 .t set
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:: M10.5 begin M00.5 SDA0 SCL until. begin Mt3 SDA0 SCL 0=until. 2 .t set
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M10.6 j
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:: MP0 MP j
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:: Mt0 Mt j
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: (warm)
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:: M00.0 clra
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begin M10.0 SDA1 SCL until. begin MP0 SDA1 SCL 0=until.
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:: M00.1 begin M10.1 SDA1 SCL until. begin MP0 SDA1 SCL 0=until.
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:: M00.2 begin M10.2 SDA1 SCL until. begin MP0 SDA1 SCL 0=until.
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M00.3 j
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:: M10.0 clra
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begin M00.0 SDA0 SCL until. begin Mt0 SDA0 SCL 0=until. 7 .t set
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:: M10.1 begin M00.1 SDA0 SCL until. begin Mt0 SDA0 SCL 0=until. 6 .t set
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:: M10.2 begin M00.2 SDA0 SCL until. begin Mt0 SDA0 SCL 0=until. 5 .t set
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M10.3 j
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: /monitor
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[ ET2 clr ] \ Timer 2 interrupt disable
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[ ES0 clr ] \ UART interrupt disable
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\i2chw
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t3i- t3+ \ Timer3 running, no intr
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%00000100 # P0MASK #!
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%00000100 # P0MAT #! \ SDA high
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%00010000 # P1MASK #!
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%00010000 # P1MAT #! \ SCL high
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\ constants in registers
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72 # [ 4 8 + ] #!
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$02 # EIE1 ior! \ EMAT
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;
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: \monitor
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$02 ~# EIE1 and! \ EMAT off
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[ ET2 set ] \ Timer 2 interrupt enable
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[ ES0 set ] \ UART interrupt enable
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t3i+ t3- \ Timer3 stopped, intr
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/i2chw
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;
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:m mismatch
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[
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PSW push
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RS0 set
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]
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7 (#!)
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Mt j
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m;
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here [
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CAPTURE-START xor 11 rshift 0<>
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[IF]
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cr .( Capture block cannot cross a 2K boundary)
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abort
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[THEN]
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]
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