24 lines
1.0 KiB
ReStructuredText
24 lines
1.0 KiB
ReStructuredText
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Load register from memory
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=========================
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Document conventions
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--------------------
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Notation: ``Rt, Rn`` denote ARM registers R0-R7 except where stated. ``immN`` represents an immediate
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value having a width of N bits hence ``imm5`` is constrained to the range 0-31. ``[Rn + immN]`` is the contents
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of the memory address obtained by adding Rn and the offset ``immN``. Offsets are measured in
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bytes. These instructions affect the condition flags.
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Register Load
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-------------
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* ldr(Rt, [Rn, imm7]) ``Rt = [Rn + imm7]`` Load a 32 bit word
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* ldrb(Rt, [Rn, imm5]) ``Rt = [Rn + imm5]`` Load a byte
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* ldrh(Rt, [Rn, imm6]) ``Rt = [Rn + imm6]`` Load a 16 bit half word
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Where a byte or half word is loaded, it is zero-extended to 32 bits.
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The specified immediate offsets are measured in bytes. Hence in the case of ``ldr`` the 7 bit value
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enables 32 bit word aligned values to be accessed with a maximum offset of 31 words. In the case of ``ldrh`` the
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6 bit value enables 16 bit half-word aligned values to be accessed with a maximum offset of 31 half-words.
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