2014-11-27 20:30:33 +00:00
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#ifndef _INCLUDED_UART_H_
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#define _INCLUDED_UART_H_
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#define UART0 (0)
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#define UART1 (1)
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typedef enum {
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UART_FIVE_BITS = 0x0,
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UART_SIX_BITS = 0x1,
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UART_SEVEN_BITS = 0x2,
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UART_EIGHT_BITS = 0x3
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} UartBitsNum4Char;
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typedef enum {
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UART_ONE_STOP_BIT = 0,
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UART_ONE_HALF_STOP_BIT = BIT2,
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UART_TWO_STOP_BIT = BIT2
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} UartStopBitsNum;
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typedef enum {
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UART_NONE_BITS = 0,
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UART_ODD_BITS = 0,
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UART_EVEN_BITS = BIT4
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} UartParityMode;
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typedef enum {
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UART_STICK_PARITY_DIS = 0,
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UART_STICK_PARITY_EN = BIT3 | BIT5
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} UartExistParity;
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typedef enum {
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UART_BIT_RATE_9600 = 9600,
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UART_BIT_RATE_19200 = 19200,
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UART_BIT_RATE_38400 = 38400,
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UART_BIT_RATE_57600 = 57600,
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UART_BIT_RATE_74880 = 74880,
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UART_BIT_RATE_115200 = 115200,
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UART_BIT_RATE_230400 = 230400,
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UART_BIT_RATE_256000 = 256000,
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UART_BIT_RATE_460800 = 460800,
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UART_BIT_RATE_921600 = 921600
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} UartBautRate;
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typedef enum {
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UART_NONE_CTRL,
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UART_HARDWARE_CTRL,
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UART_XON_XOFF_CTRL
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} UartFlowCtrl;
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typedef enum {
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UART_EMPTY,
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UART_UNDER_WRITE,
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UART_WRITE_OVER
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} RcvMsgBuffState;
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typedef struct {
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uint32 RcvBuffSize;
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uint8 *pRcvMsgBuff;
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uint8 *pWritePos;
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uint8 *pReadPos;
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uint8 TrigLvl; //JLU: may need to pad
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RcvMsgBuffState BuffState;
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} RcvMsgBuff;
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typedef struct {
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uint32 TrxBuffSize;
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uint8 *pTrxBuff;
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} TrxMsgBuff;
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typedef enum {
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UART_BAUD_RATE_DET,
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UART_WAIT_SYNC_FRM,
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UART_SRCH_MSG_HEAD,
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UART_RCV_MSG_BODY,
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UART_RCV_ESC_CHAR,
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} RcvMsgState;
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typedef struct {
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UartBautRate baut_rate;
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UartBitsNum4Char data_bits;
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UartExistParity exist_parity;
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UartParityMode parity; // chip size in byte
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UartStopBitsNum stop_bits;
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UartFlowCtrl flow_ctrl;
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RcvMsgBuff rcv_buff;
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TrxMsgBuff trx_buff;
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RcvMsgState rcv_state;
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int received;
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int buff_uart_no; //indicate which uart use tx/rx buffer
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} UartDevice;
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void uart_init(UartBautRate uart0_br, UartBautRate uart1_br);
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int uart0_rx(void);
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void uart_tx_one_char(uint8 uart, uint8 TxChar);
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2016-01-03 05:33:42 +00:00
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void uart_flush(uint8 uart);
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2014-11-27 20:30:33 +00:00
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#endif // _INCLUDED_UART_H_
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