2014-11-27 20:30:33 +00:00
|
|
|
/******************************************************************************
|
|
|
|
* Copyright 2013-2014 Espressif Systems (Wuxi)
|
|
|
|
*
|
|
|
|
* FileName: uart.c
|
|
|
|
*
|
|
|
|
* Description: Two UART mode configration and interrupt handler.
|
|
|
|
* Check your hardware connection while use this mode.
|
|
|
|
*
|
|
|
|
* Modification history:
|
|
|
|
* 2014/3/12, v1.0 create this file.
|
|
|
|
*******************************************************************************/
|
|
|
|
#include "ets_sys.h"
|
|
|
|
#include "osapi.h"
|
|
|
|
#include "uart.h"
|
|
|
|
#include "osapi.h"
|
|
|
|
#include "uart_register.h"
|
|
|
|
#include "etshal.h"
|
|
|
|
#include "c_types.h"
|
2015-01-15 23:54:40 +00:00
|
|
|
#include "user_interface.h"
|
|
|
|
#include "esp_mphal.h"
|
2014-11-27 20:30:33 +00:00
|
|
|
|
2016-05-29 10:30:27 +01:00
|
|
|
// seems that this is missing in the Espressif SDK
|
|
|
|
#define FUNC_U0RXD 0
|
|
|
|
|
2015-05-31 23:27:39 +01:00
|
|
|
#define UART_REPL UART0
|
2014-11-27 20:30:33 +00:00
|
|
|
|
|
|
|
// UartDev is defined and initialized in rom code.
|
|
|
|
extern UartDevice UartDev;
|
|
|
|
|
2016-04-05 22:12:58 +01:00
|
|
|
// the uart to which OS messages go; -1 to disable
|
|
|
|
static int uart_os = UART_OS;
|
|
|
|
|
2016-04-01 12:30:47 +01:00
|
|
|
#if MICROPY_REPL_EVENT_DRIVEN
|
2015-01-15 23:54:40 +00:00
|
|
|
static os_event_t uart_evt_queue[16];
|
2016-04-01 12:30:47 +01:00
|
|
|
#endif
|
2015-01-15 23:54:40 +00:00
|
|
|
|
2018-05-15 06:13:58 +01:00
|
|
|
// A small, static ring buffer for incoming chars
|
|
|
|
// This will only be populated if the UART is not attached to dupterm
|
2018-12-05 12:31:24 +00:00
|
|
|
uint8 uart_ringbuf_array[UART0_STATIC_RXBUF_LEN];
|
2018-05-15 06:13:58 +01:00
|
|
|
static ringbuf_t uart_ringbuf = {uart_ringbuf_array, sizeof(uart_ringbuf_array), 0, 0};
|
|
|
|
|
2014-11-27 20:30:33 +00:00
|
|
|
static void uart0_rx_intr_handler(void *para);
|
|
|
|
|
2016-04-01 12:53:01 +01:00
|
|
|
void soft_reset(void);
|
|
|
|
void mp_keyboard_interrupt(void);
|
|
|
|
|
2014-11-27 20:30:33 +00:00
|
|
|
/******************************************************************************
|
|
|
|
* FunctionName : uart_config
|
|
|
|
* Description : Internal used function
|
|
|
|
* UART0 used for data TX/RX, RX buffer size is 0x100, interrupt enabled
|
|
|
|
* UART1 just used for debug output
|
|
|
|
* Parameters : uart_no, use UART0 or UART1 defined ahead
|
|
|
|
* Returns : NONE
|
|
|
|
*******************************************************************************/
|
|
|
|
static void ICACHE_FLASH_ATTR uart_config(uint8 uart_no) {
|
|
|
|
if (uart_no == UART1) {
|
|
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
|
|
|
|
} else {
|
|
|
|
ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, NULL);
|
|
|
|
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
|
|
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
|
2016-05-29 10:30:27 +01:00
|
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD);
|
2014-11-27 20:30:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate));
|
|
|
|
|
|
|
|
WRITE_PERI_REG(UART_CONF0(uart_no), UartDev.exist_parity
|
|
|
|
| UartDev.parity
|
|
|
|
| (UartDev.stop_bits << UART_STOP_BIT_NUM_S)
|
|
|
|
| (UartDev.data_bits << UART_BIT_NUM_S));
|
|
|
|
|
|
|
|
// clear rx and tx fifo,not ready
|
|
|
|
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
|
|
|
|
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
|
|
|
|
|
|
|
|
if (uart_no == UART0) {
|
|
|
|
// set rx fifo trigger
|
|
|
|
WRITE_PERI_REG(UART_CONF1(uart_no),
|
|
|
|
((0x10 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) |
|
|
|
|
((0x10 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) |
|
|
|
|
UART_RX_FLOW_EN |
|
|
|
|
(0x02 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S |
|
|
|
|
UART_RX_TOUT_EN);
|
|
|
|
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_TOUT_INT_ENA |
|
|
|
|
UART_FRM_ERR_INT_ENA);
|
|
|
|
} else {
|
|
|
|
WRITE_PERI_REG(UART_CONF1(uart_no),
|
|
|
|
((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
|
|
|
|
}
|
|
|
|
|
|
|
|
// clear all interrupt
|
|
|
|
WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff);
|
|
|
|
// enable rx_interrupt
|
|
|
|
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA);
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************************
|
|
|
|
* FunctionName : uart1_tx_one_char
|
|
|
|
* Description : Internal used function
|
|
|
|
* Use uart1 interface to transfer one char
|
|
|
|
* Parameters : uint8 TxChar - character to tx
|
|
|
|
* Returns : OK
|
|
|
|
*******************************************************************************/
|
|
|
|
void uart_tx_one_char(uint8 uart, uint8 TxChar) {
|
|
|
|
while (true) {
|
|
|
|
uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT<<UART_TXFIFO_CNT_S);
|
|
|
|
if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
WRITE_PERI_REG(UART_FIFO(uart), TxChar);
|
|
|
|
}
|
|
|
|
|
2016-01-03 05:33:42 +00:00
|
|
|
void uart_flush(uint8 uart) {
|
|
|
|
while (true) {
|
|
|
|
uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT<<UART_TXFIFO_CNT_S);
|
|
|
|
if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) == 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-27 20:30:33 +00:00
|
|
|
/******************************************************************************
|
|
|
|
* FunctionName : uart1_write_char
|
|
|
|
* Description : Internal used function
|
|
|
|
* Do some special deal while tx char is '\r' or '\n'
|
|
|
|
* Parameters : char c - character to tx
|
|
|
|
* Returns : NONE
|
|
|
|
*******************************************************************************/
|
|
|
|
static void ICACHE_FLASH_ATTR
|
2015-05-13 14:39:25 +01:00
|
|
|
uart_os_write_char(char c) {
|
2016-04-05 22:12:58 +01:00
|
|
|
if (uart_os == -1) {
|
|
|
|
return;
|
|
|
|
}
|
2014-11-27 20:30:33 +00:00
|
|
|
if (c == '\n') {
|
2016-04-05 22:12:58 +01:00
|
|
|
uart_tx_one_char(uart_os, '\r');
|
|
|
|
uart_tx_one_char(uart_os, '\n');
|
2014-11-27 20:30:33 +00:00
|
|
|
} else if (c == '\r') {
|
|
|
|
} else {
|
2016-04-05 22:12:58 +01:00
|
|
|
uart_tx_one_char(uart_os, c);
|
2014-11-27 20:30:33 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-05 22:12:58 +01:00
|
|
|
void ICACHE_FLASH_ATTR
|
|
|
|
uart_os_config(int uart) {
|
|
|
|
uart_os = uart;
|
|
|
|
}
|
|
|
|
|
2014-11-27 20:30:33 +00:00
|
|
|
/******************************************************************************
|
|
|
|
* FunctionName : uart0_rx_intr_handler
|
|
|
|
* Description : Internal used function
|
|
|
|
* UART0 interrupt handler, add self handle code inside
|
|
|
|
* Parameters : void *para - point to ETS_UART_INTR_ATTACH's arg
|
|
|
|
* Returns : NONE
|
|
|
|
*******************************************************************************/
|
|
|
|
|
|
|
|
static void uart0_rx_intr_handler(void *para) {
|
|
|
|
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
|
|
|
|
* uart1 and uart0 respectively
|
|
|
|
*/
|
|
|
|
|
2015-05-31 23:27:39 +01:00
|
|
|
uint8 uart_no = UART_REPL;
|
2014-11-27 20:30:33 +00:00
|
|
|
|
|
|
|
if (UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_FRM_ERR_INT_ST)) {
|
|
|
|
// frame error
|
|
|
|
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) {
|
|
|
|
// fifo full
|
|
|
|
goto read_chars;
|
|
|
|
} else if (UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST)) {
|
|
|
|
read_chars:
|
2015-05-31 23:27:39 +01:00
|
|
|
ETS_UART_INTR_DISABLE();
|
2016-03-30 16:50:38 +01:00
|
|
|
|
|
|
|
while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
|
|
|
|
uint8 RcvChar = READ_PERI_REG(UART_FIFO(uart_no)) & 0xff;
|
2018-05-15 06:13:58 +01:00
|
|
|
// For efficiency, when connected to dupterm we put incoming chars
|
|
|
|
// directly on stdin_ringbuf, rather than going via uart_ringbuf
|
|
|
|
if (uart_attached_to_dupterm) {
|
|
|
|
if (RcvChar == mp_interrupt_char) {
|
|
|
|
mp_keyboard_interrupt();
|
|
|
|
} else {
|
|
|
|
ringbuf_put(&stdin_ringbuf, RcvChar);
|
|
|
|
}
|
2016-04-01 12:53:01 +01:00
|
|
|
} else {
|
2018-05-15 06:13:58 +01:00
|
|
|
ringbuf_put(&uart_ringbuf, RcvChar);
|
2016-04-01 12:53:01 +01:00
|
|
|
}
|
2016-03-30 16:50:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// Clear pending FIFO interrupts
|
|
|
|
WRITE_PERI_REG(UART_INT_CLR(UART_REPL), UART_RXFIFO_TOUT_INT_CLR | UART_RXFIFO_FULL_INT_ST);
|
|
|
|
ETS_UART_INTR_ENABLE();
|
2018-05-15 06:13:58 +01:00
|
|
|
|
|
|
|
if (uart_attached_to_dupterm) {
|
|
|
|
mp_hal_signal_input();
|
|
|
|
}
|
2014-11-27 20:30:33 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-21 15:19:00 +01:00
|
|
|
// Waits at most timeout microseconds for at least 1 char to become ready for reading.
|
|
|
|
// Returns true if something available, false if not.
|
|
|
|
bool uart_rx_wait(uint32_t timeout_us) {
|
|
|
|
uint32_t start = system_get_time();
|
|
|
|
for (;;) {
|
2018-05-15 06:13:58 +01:00
|
|
|
if (uart_ringbuf.iget != uart_ringbuf.iput) {
|
2016-04-21 15:19:00 +01:00
|
|
|
return true; // have at least 1 char ready for reading
|
|
|
|
}
|
|
|
|
if (system_get_time() - start >= timeout_us) {
|
|
|
|
return false; // timeout
|
|
|
|
}
|
|
|
|
ets_event_poll();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-01-30 02:48:55 +00:00
|
|
|
int uart_rx_any(uint8 uart) {
|
2018-05-15 06:13:58 +01:00
|
|
|
if (uart_ringbuf.iget != uart_ringbuf.iput) {
|
2017-01-30 02:48:55 +00:00
|
|
|
return true; // have at least 1 char ready for reading
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
int uart_tx_any_room(uint8 uart) {
|
|
|
|
uint32_t fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
|
|
|
|
if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) >= 126) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-04-21 15:19:00 +01:00
|
|
|
// Returns char from the input buffer, else -1 if buffer is empty.
|
|
|
|
int uart_rx_char(void) {
|
2018-05-15 06:13:58 +01:00
|
|
|
return ringbuf_get(&uart_ringbuf);
|
2016-04-21 15:19:00 +01:00
|
|
|
}
|
|
|
|
|
2015-05-31 23:27:39 +01:00
|
|
|
int uart_rx_one_char(uint8 uart_no) {
|
|
|
|
if (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
|
|
|
|
return READ_PERI_REG(UART_FIFO(uart_no)) & 0xff;
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2014-11-27 20:30:33 +00:00
|
|
|
/******************************************************************************
|
|
|
|
* FunctionName : uart_init
|
|
|
|
* Description : user interface for init uart
|
|
|
|
* Parameters : UartBautRate uart0_br - uart0 bautrate
|
|
|
|
* UartBautRate uart1_br - uart1 bautrate
|
|
|
|
* Returns : NONE
|
|
|
|
*******************************************************************************/
|
|
|
|
void ICACHE_FLASH_ATTR uart_init(UartBautRate uart0_br, UartBautRate uart1_br) {
|
|
|
|
// rom use 74880 baut_rate, here reinitialize
|
|
|
|
UartDev.baut_rate = uart0_br;
|
|
|
|
uart_config(UART0);
|
|
|
|
UartDev.baut_rate = uart1_br;
|
|
|
|
uart_config(UART1);
|
|
|
|
ETS_UART_INTR_ENABLE();
|
|
|
|
|
2016-03-29 19:10:10 +01:00
|
|
|
// install handler for "os" messages
|
2015-05-13 14:39:25 +01:00
|
|
|
os_install_putc1((void *)uart_os_write_char);
|
2014-11-27 20:30:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void ICACHE_FLASH_ATTR uart_reattach() {
|
|
|
|
uart_init(UART_BIT_RATE_74880, UART_BIT_RATE_74880);
|
|
|
|
}
|
2015-01-15 23:54:40 +00:00
|
|
|
|
2016-06-29 13:18:48 +01:00
|
|
|
void ICACHE_FLASH_ATTR uart_setup(uint8 uart) {
|
|
|
|
ETS_UART_INTR_DISABLE();
|
|
|
|
uart_config(uart);
|
|
|
|
ETS_UART_INTR_ENABLE();
|
|
|
|
}
|
|
|
|
|
2018-12-05 12:31:24 +00:00
|
|
|
int ICACHE_FLASH_ATTR uart0_get_rxbuf_len(void) {
|
|
|
|
return uart_ringbuf.size;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ICACHE_FLASH_ATTR uart0_set_rxbuf(uint8 *buf, int len) {
|
|
|
|
ETS_UART_INTR_DISABLE();
|
|
|
|
uart_ringbuf.buf = buf;
|
|
|
|
uart_ringbuf.size = len;
|
|
|
|
uart_ringbuf.iget = 0;
|
|
|
|
uart_ringbuf.iput = 0;
|
|
|
|
ETS_UART_INTR_ENABLE();
|
|
|
|
}
|
|
|
|
|
2015-01-15 23:54:40 +00:00
|
|
|
// Task-based UART interface
|
|
|
|
|
2015-05-06 00:02:58 +01:00
|
|
|
#include "py/obj.h"
|
2015-11-09 13:13:09 +00:00
|
|
|
#include "lib/utils/pyexec.h"
|
2015-05-06 00:02:58 +01:00
|
|
|
|
2016-04-01 12:02:36 +01:00
|
|
|
#if MICROPY_REPL_EVENT_DRIVEN
|
2015-01-15 23:54:40 +00:00
|
|
|
void uart_task_handler(os_event_t *evt) {
|
2016-04-01 10:53:50 +01:00
|
|
|
if (pyexec_repl_active) {
|
|
|
|
// TODO: Just returning here isn't exactly right.
|
|
|
|
// What really should be done is something like
|
|
|
|
// enquing delayed event to itself, for another
|
|
|
|
// chance to feed data to REPL. Otherwise, there
|
|
|
|
// can be situation when buffer has bunch of data,
|
|
|
|
// and sits unprocessed, because we consumed all
|
|
|
|
// processing signals like this.
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-05-31 23:27:39 +01:00
|
|
|
int c, ret = 0;
|
2019-06-14 21:22:03 +01:00
|
|
|
while ((c = ringbuf_get(&stdin_ringbuf)) >= 0) {
|
2018-02-26 05:09:33 +00:00
|
|
|
if (c == mp_interrupt_char) {
|
2015-12-20 11:58:58 +00:00
|
|
|
mp_keyboard_interrupt();
|
|
|
|
}
|
2015-05-31 23:27:39 +01:00
|
|
|
ret = pyexec_event_repl_process_char(c);
|
|
|
|
if (ret & PYEXEC_FORCED_EXIT) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-05-06 00:02:58 +01:00
|
|
|
if (ret & PYEXEC_FORCED_EXIT) {
|
|
|
|
soft_reset();
|
|
|
|
}
|
2015-01-15 23:54:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void uart_task_init() {
|
|
|
|
system_os_task(uart_task_handler, UART_TASK_ID, uart_evt_queue, sizeof(uart_evt_queue) / sizeof(*uart_evt_queue));
|
|
|
|
}
|
2016-04-01 12:02:36 +01:00
|
|
|
#endif
|