2015-02-13 15:04:53 +00:00
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#include <string.h>
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2014-10-23 14:25:32 +01:00
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2016-10-07 03:58:25 +01:00
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#include "py/runtime.h"
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2019-06-19 05:02:38 +01:00
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#include "py/stream.h"
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2016-05-10 23:22:54 +01:00
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#include "py/mperrno.h"
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2015-10-30 23:03:58 +00:00
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#include "py/mphal.h"
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2017-10-19 04:16:42 +01:00
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#include "extmod/misc.h"
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2014-11-27 16:58:31 +00:00
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#include "usb.h"
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2015-02-13 15:04:53 +00:00
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#include "uart.h"
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2014-10-23 14:25:32 +01:00
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// this table converts from HAL_StatusTypeDef to POSIX errno
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const byte mp_hal_status_to_errno_table[4] = {
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[HAL_OK] = 0,
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2016-05-10 23:22:54 +01:00
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[HAL_ERROR] = MP_EIO,
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[HAL_BUSY] = MP_EBUSY,
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[HAL_TIMEOUT] = MP_ETIMEDOUT,
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2014-10-23 14:25:32 +01:00
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};
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NORETURN void mp_hal_raise(HAL_StatusTypeDef status) {
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2016-10-07 03:58:25 +01:00
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mp_raise_OSError(mp_hal_status_to_errno_table[status]);
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2014-10-23 14:25:32 +01:00
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}
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2014-11-27 16:58:31 +00:00
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2019-06-19 05:02:38 +01:00
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MP_WEAK uintptr_t mp_hal_stdio_poll(uintptr_t poll_flags) {
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uintptr_t ret = 0;
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if (MP_STATE_PORT(pyb_stdio_uart) != NULL) {
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2019-12-27 11:46:43 +00:00
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mp_obj_t pyb_stdio_uart = MP_OBJ_FROM_PTR(MP_STATE_PORT(pyb_stdio_uart));
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2019-06-19 05:02:38 +01:00
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int errcode;
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2019-12-27 11:46:43 +00:00
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const mp_stream_p_t *stream_p = mp_get_stream(pyb_stdio_uart);
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ret = stream_p->ioctl(pyb_stdio_uart, MP_STREAM_POLL, poll_flags, &errcode);
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2019-06-19 05:02:38 +01:00
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}
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return ret | mp_uos_dupterm_poll(poll_flags);
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}
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2018-07-17 19:22:35 +01:00
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MP_WEAK int mp_hal_stdin_rx_chr(void) {
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2015-02-13 15:04:53 +00:00
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for (;;) {
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#if 0
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#ifdef USE_HOST_MODE
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pyb_usb_host_process();
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int c = pyb_usb_host_get_keyboard();
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if (c != 0) {
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return c;
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}
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#endif
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#endif
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2018-02-13 07:51:08 +00:00
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if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) {
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2015-02-13 15:04:53 +00:00
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return uart_rx_char(MP_STATE_PORT(pyb_stdio_uart));
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}
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2017-10-19 04:16:42 +01:00
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int dupterm_c = mp_uos_dupterm_rx_chr();
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if (dupterm_c >= 0) {
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return dupterm_c;
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}
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2017-02-06 04:10:03 +00:00
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MICROPY_EVENT_POLL_HOOK
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2015-02-13 15:04:53 +00:00
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}
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}
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2018-07-17 19:22:35 +01:00
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MP_WEAK void mp_hal_stdout_tx_strn(const char *str, size_t len) {
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2015-02-13 15:04:53 +00:00
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if (MP_STATE_PORT(pyb_stdio_uart) != NULL) {
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uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len);
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}
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#if 0 && defined(USE_HOST_MODE) && MICROPY_HW_HAS_LCD
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lcd_print_strn(str, len);
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#endif
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2017-10-19 04:16:42 +01:00
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mp_uos_dupterm_tx_strn(str, len);
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2015-02-13 15:04:53 +00:00
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}
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2018-05-28 02:23:33 +01:00
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#if __CORTEX_M >= 0x03
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2016-10-18 04:30:00 +01:00
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void mp_hal_ticks_cpu_enable(void) {
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2018-03-29 06:23:52 +01:00
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if (!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) {
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2016-10-18 04:30:00 +01:00
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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2017-03-10 03:58:26 +00:00
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#if defined(__CORTEX_M) && __CORTEX_M == 7
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// on Cortex-M7 we must unlock the DWT before writing to its registers
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DWT->LAR = 0xc5acce55;
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#endif
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2016-10-18 04:30:00 +01:00
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DWT->CYCCNT = 0;
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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}
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}
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2018-05-28 02:23:33 +01:00
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#endif
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2016-10-18 04:30:00 +01:00
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2015-08-03 00:05:16 +01:00
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void mp_hal_gpio_clock_enable(GPIO_TypeDef *gpio) {
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2018-05-18 08:03:53 +01:00
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#if defined(STM32L476xx) || defined(STM32L496xx)
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2018-05-02 04:08:58 +01:00
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if (gpio == GPIOG) {
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2017-01-11 17:26:33 +00:00
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// Port G pins 2 thru 15 are powered using VddIO2 on these MCUs.
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HAL_PWREx_EnableVddIO2();
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2018-05-02 04:08:58 +01:00
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}
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2015-08-03 00:05:16 +01:00
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#endif
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2018-05-02 04:08:58 +01:00
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// This logic assumes that all the GPIOx_EN bits are adjacent and ordered in one register
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2022-09-19 09:56:31 +01:00
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#if defined(STM32F0) || defined(STM32L1)
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2018-05-28 09:10:53 +01:00
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#define AHBxENR AHBENR
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#define AHBxENR_GPIOAEN_Pos RCC_AHBENR_GPIOAEN_Pos
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#elif defined(STM32F4) || defined(STM32F7)
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2018-05-02 04:08:58 +01:00
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#define AHBxENR AHB1ENR
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#define AHBxENR_GPIOAEN_Pos RCC_AHB1ENR_GPIOAEN_Pos
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#elif defined(STM32H7)
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#define AHBxENR AHB4ENR
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#define AHBxENR_GPIOAEN_Pos RCC_AHB4ENR_GPIOAEN_Pos
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2019-07-05 08:24:59 +01:00
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#elif defined(STM32L0)
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#define AHBxENR IOPENR
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2019-07-16 05:47:12 +01:00
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#define AHBxENR_GPIOAEN_Pos RCC_IOPENR_IOPAEN_Pos
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2022-02-12 20:36:58 +00:00
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#elif defined(STM32G0)
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#define AHBxENR IOPENR
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#define AHBxENR_GPIOAEN_Pos RCC_IOPENR_GPIOAEN_Pos
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2021-02-22 00:55:12 +00:00
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#elif defined(STM32G4) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
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2018-05-02 04:08:58 +01:00
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#define AHBxENR AHB2ENR
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#define AHBxENR_GPIOAEN_Pos RCC_AHB2ENR_GPIOAEN_Pos
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2015-08-03 00:05:16 +01:00
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#endif
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2018-05-02 04:08:58 +01:00
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uint32_t gpio_idx = ((uint32_t)gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
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RCC->AHBxENR |= 1 << (AHBxENR_GPIOAEN_Pos + gpio_idx);
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volatile uint32_t tmp = RCC->AHBxENR; // Delay after enabling clock
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(void)tmp;
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2015-08-03 00:05:16 +01:00
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}
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2016-02-11 05:20:14 +00:00
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2016-10-18 04:32:42 +01:00
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void mp_hal_pin_config(mp_hal_pin_obj_t pin_obj, uint32_t mode, uint32_t pull, uint32_t alt) {
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GPIO_TypeDef *gpio = pin_obj->gpio;
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uint32_t pin = pin_obj->pin;
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2016-04-12 13:50:47 +01:00
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mp_hal_gpio_clock_enable(gpio);
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2022-04-13 15:54:01 +01:00
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if (mode == MP_HAL_PIN_MODE_ALT || mode == MP_HAL_PIN_MODE_ALT_OPEN_DRAIN) {
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// To avoid any I/O glitches, make sure a valid alternate function is set in
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// AFR first before switching the pin mode. When switching from AF to INPUT or
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// OUTPUT, the AF in AFR will remain valid up until the pin mode is switched.
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gpio->AFR[pin >> 3] = (gpio->AFR[pin >> 3] & ~(15 << (4 * (pin & 7)))) | (alt << (4 * (pin & 7)));
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}
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2016-04-12 13:50:47 +01:00
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gpio->MODER = (gpio->MODER & ~(3 << (2 * pin))) | ((mode & 3) << (2 * pin));
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2018-05-02 03:05:45 +01:00
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#if defined(GPIO_ASCR_ASC0)
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// The L4 has a special analog switch to connect the GPIO to the ADC
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gpio->OTYPER = (gpio->OTYPER & ~(1 << pin)) | (((mode >> 2) & 1) << pin);
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gpio->ASCR = (gpio->ASCR & ~(1 << pin)) | ((mode >> 3) & 1) << pin;
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#else
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2016-04-12 13:50:47 +01:00
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gpio->OTYPER = (gpio->OTYPER & ~(1 << pin)) | ((mode >> 2) << pin);
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2018-05-02 03:05:45 +01:00
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#endif
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2016-04-12 13:50:47 +01:00
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gpio->OSPEEDR = (gpio->OSPEEDR & ~(3 << (2 * pin))) | (2 << (2 * pin)); // full speed
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gpio->PUPDR = (gpio->PUPDR & ~(3 << (2 * pin))) | (pull << (2 * pin));
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}
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2016-11-11 06:53:45 +00:00
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bool mp_hal_pin_config_alt(mp_hal_pin_obj_t pin, uint32_t mode, uint32_t pull, uint8_t fn, uint8_t unit) {
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2016-02-11 05:20:14 +00:00
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const pin_af_obj_t *af = pin_find_af(pin, fn, unit);
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if (af == NULL) {
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return false;
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}
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2016-11-11 06:53:45 +00:00
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mp_hal_pin_config(pin, mode, pull, af->idx);
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2016-02-11 05:20:14 +00:00
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return true;
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}
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2018-05-01 08:31:23 +01:00
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void mp_hal_pin_config_speed(mp_hal_pin_obj_t pin_obj, uint32_t speed) {
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GPIO_TypeDef *gpio = pin_obj->gpio;
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uint32_t pin = pin_obj->pin;
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gpio->OSPEEDR = (gpio->OSPEEDR & ~(3 << (2 * pin))) | (speed << (2 * pin));
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}
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2019-02-22 10:53:41 +00:00
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2019-06-01 07:08:40 +01:00
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/*******************************************************************************/
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// MAC address
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2019-08-21 14:06:56 +01:00
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// Generate a random locally administered MAC address (LAA)
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void mp_hal_generate_laa_mac(int idx, uint8_t buf[6]) {
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2019-02-22 10:53:41 +00:00
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uint8_t *id = (uint8_t *)MP_HAL_UNIQUE_ID_ADDRESS;
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buf[0] = 0x02; // LAA range
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buf[1] = (id[11] << 4) | (id[10] & 0xf);
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buf[2] = (id[9] << 4) | (id[8] & 0xf);
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buf[3] = (id[7] << 4) | (id[6] & 0xf);
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buf[4] = id[2];
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buf[5] = (id[0] << 2) | idx;
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}
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2019-06-01 07:08:40 +01:00
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2019-08-21 14:06:56 +01:00
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// A board can override this if needed
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MP_WEAK void mp_hal_get_mac(int idx, uint8_t buf[6]) {
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mp_hal_generate_laa_mac(idx, buf);
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}
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2019-06-01 07:08:40 +01:00
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void mp_hal_get_mac_ascii(int idx, size_t chr_off, size_t chr_len, char *dest) {
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static const char hexchr[16] = "0123456789ABCDEF";
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uint8_t mac[6];
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mp_hal_get_mac(idx, mac);
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for (; chr_len; ++chr_off, --chr_len) {
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*dest++ = hexchr[mac[chr_off >> 1] >> (4 * (1 - (chr_off & 1))) & 0xf];
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}
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}
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2022-07-01 20:48:59 +01:00
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MP_REGISTER_ROOT_POINTER(struct _pyb_uart_obj_t *pyb_stdio_uart);
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