2015-04-10 20:02:07 +01:00
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/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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* Copyright (c) 2015 Daniel Campora
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2015-09-27 12:45:48 +01:00
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// for machine module
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2015-12-18 00:35:33 +00:00
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Q(umachine)
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2015-09-25 14:20:07 +01:00
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#ifdef DEBUG
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2015-02-06 14:35:48 +00:00
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Q(info)
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2015-09-25 14:20:07 +01:00
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#endif
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2015-06-10 18:30:56 +01:00
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Q(reset)
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2015-02-06 14:35:48 +00:00
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Q(main)
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Q(sync)
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Q(rng)
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Q(freq)
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2015-05-29 09:22:20 +01:00
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Q(unique_id)
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2015-02-06 14:35:48 +00:00
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Q(disable_irq)
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Q(enable_irq)
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2015-09-27 12:45:48 +01:00
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Q(idle)
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Q(sleep)
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Q(deepsleep)
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Q(reset_cause)
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Q(wake_reason)
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Q(IDLE)
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Q(SLEEP)
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Q(DEEPSLEEP)
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Q(POWER_ON)
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Q(HARD_RESET)
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Q(WDT_RESET)
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Q(DEEPSLEEP_RESET)
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Q(SOFT_RESET)
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Q(WLAN_WAKE)
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Q(PIN_WAKE)
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Q(RTC_WAKE)
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2015-09-25 14:20:07 +01:00
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2015-10-14 08:46:18 +01:00
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// for wipy module
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Q(wipy)
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Q(heartbeat)
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2015-09-16 13:09:51 +01:00
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// entries for sys.path
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2015-04-10 20:02:07 +01:00
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Q(/flash)
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Q(/flash/lib)
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2015-02-06 14:35:48 +00:00
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2015-09-27 12:45:48 +01:00
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// interactive help
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Q(help)
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2015-02-06 14:35:48 +00:00
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// for module weak links
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2015-07-10 08:19:59 +01:00
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Q(struct)
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2015-05-07 11:16:55 +01:00
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Q(binascii)
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2015-02-06 14:35:48 +00:00
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Q(re)
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Q(json)
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Q(heapq)
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2015-09-27 17:04:11 +01:00
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//Q(hashlib)
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2015-02-06 14:35:48 +00:00
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// for os module
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Q(os)
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2015-09-16 13:09:51 +01:00
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Q(uos)
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2015-04-28 18:53:45 +01:00
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Q(sysname)
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Q(nodename)
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Q(release)
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Q(version)
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Q(machine)
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Q(uname)
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2015-02-06 14:35:48 +00:00
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Q(/)
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2015-04-10 20:02:07 +01:00
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Q(flash)
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2015-02-06 14:35:48 +00:00
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Q(chdir)
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Q(getcwd)
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Q(listdir)
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Q(mkdir)
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2015-05-13 14:06:11 +01:00
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Q(rename)
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2015-02-06 14:35:48 +00:00
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Q(remove)
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Q(rmdir)
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Q(unlink)
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Q(sep)
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Q(stat)
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Q(urandom)
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2015-06-10 21:24:47 +01:00
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Q(mkfs)
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2015-09-16 13:09:51 +01:00
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Q(mount)
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Q(unmount)
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2015-09-25 14:20:07 +01:00
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Q(dupterm)
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2015-09-16 13:09:51 +01:00
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Q(readonly)
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Q(readblocks)
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Q(writeblocks)
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Q(sync)
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Q(count)
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2015-02-06 14:35:48 +00:00
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// for file class
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Q(seek)
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Q(tell)
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2015-09-25 14:20:07 +01:00
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Q(input)
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Q(flush)
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2015-02-06 14:35:48 +00:00
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2015-02-09 18:38:02 +00:00
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// for Pin class
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Q(Pin)
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2015-08-18 13:07:19 +01:00
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Q(board)
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2015-02-06 14:35:48 +00:00
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Q(init)
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Q(value)
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2015-05-02 21:57:51 +01:00
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Q(toggle)
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2015-08-18 13:07:19 +01:00
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Q(id)
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2015-02-06 14:35:48 +00:00
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Q(mode)
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2015-08-18 13:07:19 +01:00
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Q(pull)
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Q(drive)
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2015-08-23 12:52:31 +01:00
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Q(alt)
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2015-09-07 08:23:46 +01:00
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Q(alt_list)
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2015-02-06 14:35:48 +00:00
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Q(IN)
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Q(OUT)
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2015-08-18 13:07:19 +01:00
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Q(OPEN_DRAIN)
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Q(ALT)
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Q(ALT_OPEN_DRAIN)
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Q(PULL_UP)
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Q(PULL_DOWN)
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Q(LOW_POWER)
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Q(MED_POWER)
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Q(HIGH_POWER)
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2015-09-03 10:25:44 +01:00
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Q(IRQ_RISING)
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Q(IRQ_FALLING)
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Q(IRQ_LOW_LEVEL)
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Q(IRQ_HIGH_LEVEL)
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2015-02-06 14:35:48 +00:00
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// for UART class
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Q(UART)
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2015-09-07 08:23:46 +01:00
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Q(init)
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Q(deinit)
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Q(any)
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Q(sendbreak)
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2015-09-11 08:33:19 +01:00
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Q(id)
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2015-02-06 14:35:48 +00:00
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Q(baudrate)
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Q(bits)
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Q(stop)
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Q(parity)
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2015-09-07 08:23:46 +01:00
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Q(pins)
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2015-09-13 14:59:45 +01:00
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Q(EVEN)
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Q(ODD)
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2015-09-07 08:23:46 +01:00
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Q(RX_ANY)
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2015-02-06 14:35:48 +00:00
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2015-02-10 12:11:27 +00:00
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// for I2C class
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Q(I2C)
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2015-09-11 10:05:58 +01:00
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Q(id)
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2015-05-25 20:06:45 +01:00
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Q(mode)
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Q(baudrate)
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2015-09-08 14:08:33 +01:00
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Q(pins)
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2015-02-10 12:11:27 +00:00
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Q(addr)
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2015-09-08 14:08:33 +01:00
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Q(nbytes)
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Q(buf)
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Q(stop)
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2015-02-10 12:11:27 +00:00
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Q(memaddr)
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2015-09-08 14:08:33 +01:00
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Q(addrsize)
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2015-02-10 12:11:27 +00:00
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Q(init)
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Q(deinit)
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Q(scan)
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2015-09-08 14:08:33 +01:00
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Q(readfrom)
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Q(readfrom_into)
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Q(writeto)
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Q(readfrom_mem)
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Q(readfrom_mem_into)
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Q(writeto_mem)
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2015-05-25 20:06:45 +01:00
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Q(MASTER)
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2015-02-10 12:11:27 +00:00
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2015-02-19 20:03:21 +00:00
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// for ADC class
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Q(ADC)
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2015-09-14 19:03:32 +01:00
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Q(ADCChannel)
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Q(value)
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2015-08-10 15:44:20 +01:00
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Q(init)
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Q(deinit)
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2015-09-14 19:03:32 +01:00
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Q(channel)
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Q(id)
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Q(pin)
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2015-02-19 20:03:21 +00:00
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2015-02-21 13:10:33 +00:00
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// for SD class
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Q(SD)
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2015-08-11 15:06:43 +01:00
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Q(init)
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Q(deinit)
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2015-09-16 13:09:51 +01:00
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Q(id)
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Q(pins)
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2015-02-21 13:10:33 +00:00
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2015-02-06 14:35:48 +00:00
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// for RTC class
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Q(RTC)
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2015-09-26 21:55:24 +01:00
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Q(id)
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2015-09-16 13:09:51 +01:00
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Q(init)
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Q(alarm)
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Q(alarm_left)
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2015-09-22 22:20:29 +01:00
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Q(alarm_cancel)
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2015-09-16 13:09:51 +01:00
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Q(now)
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Q(deinit)
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2015-02-06 14:35:48 +00:00
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Q(datetime)
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2015-09-16 13:09:51 +01:00
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Q(repeat)
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2015-09-22 22:20:29 +01:00
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Q(ALARM0)
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2015-02-06 14:35:48 +00:00
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// for time class
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2015-09-16 13:09:51 +01:00
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Q(time)
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2015-02-06 14:35:48 +00:00
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Q(utime)
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Q(localtime)
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Q(mktime)
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Q(sleep)
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2015-09-16 13:09:51 +01:00
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Q(sleep_ms)
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Q(sleep_us)
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Q(ticks_ms)
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Q(ticks_us)
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Q(ticks_cpu)
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Q(ticks_diff)
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2015-02-06 14:35:48 +00:00
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// for select class
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Q(select)
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Q(uselect)
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Q(register)
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Q(unregister)
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Q(modify)
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Q(poll)
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2015-11-09 20:10:01 +00:00
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Q(POLLIN)
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Q(POLLOUT)
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Q(POLLERR)
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Q(POLLHUP)
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2015-02-06 14:35:48 +00:00
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// for socket class
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Q(socket)
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Q(usocket)
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Q(getaddrinfo)
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Q(family)
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Q(type)
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Q(send)
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2015-07-17 10:38:01 +01:00
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Q(sendall)
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2015-02-06 14:35:48 +00:00
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Q(sendto)
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Q(recv)
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Q(recvfrom)
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Q(listen)
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Q(accept)
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Q(bind)
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Q(settimeout)
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Q(setblocking)
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Q(setsockopt)
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Q(close)
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2015-07-28 22:06:17 +01:00
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Q(makefile)
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2015-02-06 14:35:48 +00:00
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Q(protocol)
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2015-06-29 21:49:18 +01:00
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Q(error)
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Q(timeout)
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2015-02-06 14:35:48 +00:00
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Q(AF_INET)
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Q(SOCK_STREAM)
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Q(SOCK_DGRAM)
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2015-04-13 15:42:02 +01:00
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Q(IPPROTO_SEC)
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2015-02-06 14:35:48 +00:00
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Q(IPPROTO_TCP)
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Q(IPPROTO_UDP)
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2015-06-11 19:26:24 +01:00
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// for ssl class
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Q(ssl)
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Q(ussl)
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Q(wrap_socket)
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Q(sock)
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Q(keyfile)
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Q(certfile)
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Q(server_side)
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Q(cert_reqs)
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Q(ca_certs)
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Q(SSLError)
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Q(CERT_NONE)
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Q(CERT_OPTIONAL)
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Q(CERT_REQUIRED)
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2015-02-06 14:35:48 +00:00
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// for network class
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Q(network)
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2015-10-19 10:41:29 +01:00
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Q(server)
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Q(init)
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Q(deinit)
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Q(login)
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Q(timeout)
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2015-10-19 14:19:34 +01:00
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Q(isrunning)
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2015-02-06 14:35:48 +00:00
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2015-02-22 17:43:01 +00:00
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// for WLAN class
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2015-02-06 14:35:48 +00:00
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Q(WLAN)
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2015-09-26 21:55:24 +01:00
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Q(id)
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Q(init)
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Q(mode)
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Q(auth)
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2015-02-06 14:35:48 +00:00
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Q(ssid)
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Q(bssid)
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2015-09-26 21:55:24 +01:00
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Q(mac)
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Q(antenna)
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2015-02-06 14:35:48 +00:00
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Q(scan)
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Q(connect)
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2015-02-23 10:22:15 +00:00
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Q(isconnected)
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2015-02-06 14:35:48 +00:00
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Q(disconnect)
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2015-10-14 08:45:37 +01:00
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Q(sec)
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2015-02-06 14:35:48 +00:00
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Q(channel)
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2015-04-28 22:52:26 +01:00
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Q(rssi)
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2015-02-23 10:22:15 +00:00
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Q(ifconfig)
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2015-09-26 21:55:24 +01:00
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Q(config)
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//Q(connections)
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//Q(urn)
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2015-02-06 14:35:48 +00:00
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Q(STA)
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Q(AP)
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Q(OPEN)
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Q(WEP)
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2015-08-05 12:36:29 +01:00
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Q(WPA)
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Q(WPA2)
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2015-09-26 21:55:24 +01:00
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Q(INT_ANT)
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Q(EXT_ANT)
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2015-09-22 22:20:29 +01:00
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Q(ANY_EVENT)
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2015-02-26 14:29:47 +00:00
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// for WDT class
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Q(WDT)
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2015-09-13 16:06:12 +01:00
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Q(feed)
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Q(timeout)
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2015-02-26 14:29:47 +00:00
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2015-09-22 22:20:29 +01:00
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// for irq class
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Q(irq)
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2015-03-04 12:52:39 +00:00
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Q(init)
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Q(enable)
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Q(disable)
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2015-09-22 22:20:29 +01:00
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Q(flags)
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Q(trigger)
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2015-03-04 12:52:39 +00:00
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Q(handler)
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Q(priority)
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2015-09-22 22:20:29 +01:00
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Q(wake)
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2015-03-04 12:52:39 +00:00
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2015-03-19 14:17:39 +00:00
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// for SPI class
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Q(SPI)
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2015-09-13 20:44:09 +01:00
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Q(id)
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2015-05-25 20:06:45 +01:00
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Q(mode)
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2015-03-19 14:17:39 +00:00
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Q(baudrate)
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Q(bits)
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2015-05-26 09:32:29 +01:00
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Q(polarity)
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Q(phase)
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2015-09-13 20:44:09 +01:00
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Q(firstbit)
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2015-03-19 14:17:39 +00:00
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Q(init)
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Q(deinit)
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2015-09-13 20:44:09 +01:00
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Q(write)
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Q(read)
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Q(readinto)
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Q(write_readinto)
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Q(nbytes)
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Q(buf)
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2015-05-25 20:06:45 +01:00
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Q(MASTER)
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2015-09-13 20:44:09 +01:00
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Q(MSB)
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2015-03-19 14:17:39 +00:00
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2015-05-09 16:46:16 +01:00
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// for Timer class
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Q(Timer)
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Q(TimerChannel)
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Q(init)
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Q(deinit)
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Q(freq)
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2015-05-29 14:47:07 +01:00
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Q(period)
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2015-05-09 16:46:16 +01:00
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Q(mode)
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Q(width)
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Q(channel)
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Q(polarity)
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Q(duty_cycle)
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Q(A)
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Q(B)
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Q(ONE_SHOT)
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Q(PERIODIC)
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Q(PWM)
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Q(POSITIVE)
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Q(NEGATIVE)
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2016-02-12 17:55:30 +00:00
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Q(TIMEOUT)
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Q(MATCH)
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2015-05-09 16:46:16 +01:00
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2015-05-19 23:23:13 +01:00
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// for uhashlib module
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2015-09-27 17:04:11 +01:00
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//Q(uhashlib)
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//Q(update)
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//Q(digest)
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2015-05-19 23:23:13 +01:00
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//Q(md5)
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2015-09-27 17:04:11 +01:00
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//Q(sha1)
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//Q(sha256)
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2015-05-22 08:54:10 +01:00
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// for ubinascii module
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Q(ubinascii)
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Q(hexlify)
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Q(unhexlify)
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2015-07-04 15:33:54 +01:00
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Q(a2b_base64)
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Q(b2a_base64)
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