280 lines
11 KiB
C
280 lines
11 KiB
C
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/**
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******************************************************************************
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* @file stm32f2xx_hal_rcc_ex.h
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* @author MCD Application Team
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* @version V1.0.1
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* @date 25-March-2014
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* @brief Header file of RCC HAL Extension module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F2xx_HAL_RCC_EX_H
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#define __STM32F2xx_HAL_RCC_EX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f2xx_hal_def.h"
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/** @addtogroup STM32F2xx_HAL_Driver
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* @{
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*/
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/** @addtogroup RCCEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief PLLI2S Clock structure definition
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*/
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typedef struct
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{
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uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
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This parameter must be a number between Min_Data = 192 and Max_Data = 432
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
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This parameter must be a number between Min_Data = 2 and Max_Data = 7
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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}RCC_PLLI2SInitTypeDef;
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/**
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* @brief RCC extended clocks structure definition
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*/
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typedef struct
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{
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
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This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
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uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
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This parameter can be a value of @ref RCC_RTC_Clock_Source */
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uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection
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This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
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}RCC_PeriphCLKInitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Constants
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* @{
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*/
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/** @defgroup RCCEx_Periph_Clock_Selection
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* @{
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*/
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#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
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#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000004)
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#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000008)
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#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000f))
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/**
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* @}
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*/
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/** @defgroup RCCEx_TIM_PRescaler_Selection
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* @{
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*/
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#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
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#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @brief Enables or disables the AHB1 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
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#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
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#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
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#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
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#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
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#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
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#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
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#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
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#endif /* STM32F207xx || STM32F217xx */
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/**
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* @brief Enable ETHERNET clock.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __ETH_CLK_ENABLE() do { \
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__ETHMAC_CLK_ENABLE(); \
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__ETHMACTX_CLK_ENABLE(); \
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__ETHMACRX_CLK_ENABLE(); \
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} while(0)
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/**
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* @brief Disable ETHERNET clock.
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*/
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#define __ETH_CLK_DISABLE() do { \
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__ETHMACTX_CLK_DISABLE(); \
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__ETHMACRX_CLK_DISABLE(); \
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__ETHMAC_CLK_DISABLE(); \
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} while(0)
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#endif /* STM32F207xx || STM32F217xx */
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/** @brief Enable or disable the AHB2 peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
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#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
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#endif /* STM32F207xx || STM32F217xx */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
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#define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
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#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
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#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
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#endif /* STM32F215xx || STM32F217xx */
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/** @brief Force or release AHB1 peripheral reset.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
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#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
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#endif /* STM32F207xx || STM32F217xx */
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/** @brief Force or release AHB2 peripheral reset.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
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#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
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#endif /* STM32F207xx || STM32F217xx */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
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#define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
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#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
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#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
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#endif /* STM32F215xx || STM32F217xx */
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/** @brief Force or release AHB3 peripheral reset
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*/
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/** @brief Force or release APB1 peripheral reset.
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*/
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/** @brief Force or release APB2 peripheral reset.
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*/
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/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce
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* power consumption.
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
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* @note By default, all peripheral clocks are enabled during SLEEP mode.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
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#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
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#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
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#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
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#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
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#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
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#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
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#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
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#endif /* STM32F207xx || STM32F217xx */
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/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
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* @note Peripheral clock gating in SLEEP mode can be used to further reduce
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* power consumption.
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* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
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* @note By default, all peripheral clocks are enabled during SLEEP mode.
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*/
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#if defined(STM32F207xx) || defined(STM32F217xx)
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#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
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#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
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#endif /* STM32F207xx || STM32F217xx */
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#if defined(STM32F215xx) || defined(STM32F217xx)
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#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
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#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
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#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
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#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
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#endif /* STM32F215xx || STM32F217xx */
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/* Exported functions --------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F2xx_HAL_RCC_EX_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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