108 lines
4.5 KiB
C
108 lines
4.5 KiB
C
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/*
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* Copyright 2018-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes default configuration of clocks.
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*
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*/
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void BOARD_InitBootClocks(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockRUN configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
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/* Clock outputs (values are in Hz): */
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#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
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#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
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#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
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#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
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#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
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#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 125000000UL
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#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
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#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
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#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
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#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
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#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
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#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
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#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
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#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
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#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
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#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
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#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
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#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
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#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
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#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
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#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
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/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
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*/
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extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
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/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
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*/
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extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
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/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
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*/
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extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
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/*******************************************************************************
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* API for BOARD_BootClockRUN configuration
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes configuration of clocks.
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*
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*/
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void BOARD_BootClockRUN(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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#endif /* _CLOCK_CONFIG_H_ */
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