2015-02-06 14:35:48 +00:00
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/*
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2017-06-30 08:22:17 +01:00
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* This file is part of the MicroPython project, http://micropython.org/
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2015-02-06 14:35:48 +00:00
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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* Copyright (c) 2015 Daniel Campora
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2015-02-20 15:31:30 +00:00
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#include <stdint.h>
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2015-02-06 14:35:48 +00:00
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#include <stdio.h>
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2015-02-20 15:31:30 +00:00
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#include <string.h>
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2015-02-06 14:35:48 +00:00
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2015-02-21 18:58:43 +00:00
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#include "py/runtime.h"
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2015-02-20 15:31:30 +00:00
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#include "py/objlist.h"
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2015-02-21 18:58:43 +00:00
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#include "py/stream.h"
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2015-10-30 23:03:58 +00:00
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#include "py/mphal.h"
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2021-07-09 05:19:15 +01:00
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#include "shared/runtime/interrupt_char.h"
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2015-02-06 14:35:48 +00:00
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#include "inc/hw_types.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_uart.h"
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#include "rom_map.h"
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#include "interrupt.h"
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#include "prcm.h"
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#include "uart.h"
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#include "pybuart.h"
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2015-09-22 22:20:29 +01:00
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#include "mpirq.h"
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2015-02-27 15:50:06 +00:00
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#include "pybsleep.h"
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2015-02-06 14:35:48 +00:00
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#include "osi.h"
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2015-06-09 16:14:31 +01:00
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#include "utils.h"
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2015-09-07 08:23:46 +01:00
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#include "pin.h"
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#include "pybpin.h"
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#include "pins.h"
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2015-09-25 14:20:07 +01:00
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#include "moduos.h"
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2015-02-06 14:35:48 +00:00
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/// \moduleref pyb
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/// \class UART - duplex serial communication bus
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2015-02-20 15:31:30 +00:00
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/******************************************************************************
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DEFINE CONSTANTS
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2015-09-07 08:23:46 +01:00
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*******-***********************************************************************/
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#define PYBUART_FRAME_TIME_US(baud) ((11 * 1000000) / baud)
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#define PYBUART_2_FRAMES_TIME_US(baud) (PYBUART_FRAME_TIME_US(baud) * 2)
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2015-10-21 13:54:16 +01:00
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#define PYBUART_RX_TIMEOUT_US(baud) (PYBUART_2_FRAMES_TIME_US(baud) * 8) // we need at least characters in the FIFO
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2015-09-07 08:23:46 +01:00
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#define PYBUART_TX_WAIT_US(baud) ((PYBUART_FRAME_TIME_US(baud)) + 1)
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2015-07-05 21:26:12 +01:00
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#define PYBUART_TX_MAX_TIMEOUT_MS (5)
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2015-02-20 15:31:30 +00:00
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2015-09-22 22:20:29 +01:00
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#define PYBUART_RX_BUFFER_LEN (256)
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2022-08-26 17:08:29 +01:00
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#define PYBUART_TX_BUFFER_LEN (17)
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2015-09-07 08:23:46 +01:00
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2015-09-07 20:19:11 +01:00
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// interrupt triggers
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2015-10-21 13:54:16 +01:00
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#define UART_TRIGGER_RX_ANY (0x01)
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#define UART_TRIGGER_RX_HALF (0x02)
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#define UART_TRIGGER_RX_FULL (0x04)
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#define UART_TRIGGER_TX_DONE (0x08)
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2015-09-07 20:19:11 +01:00
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2015-02-06 14:35:48 +00:00
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/******************************************************************************
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DECLARE PRIVATE FUNCTIONS
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******************************************************************************/
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2015-03-04 12:52:39 +00:00
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STATIC void uart_init (pyb_uart_obj_t *self);
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2015-09-07 08:23:46 +01:00
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STATIC bool uart_rx_wait (pyb_uart_obj_t *self);
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2015-09-07 20:19:11 +01:00
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STATIC void uart_check_init(pyb_uart_obj_t *self);
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2015-09-22 22:20:29 +01:00
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STATIC mp_obj_t uart_irq_new (pyb_uart_obj_t *self, byte trigger, mp_int_t priority, mp_obj_t handler);
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2015-02-06 14:35:48 +00:00
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STATIC void UARTGenericIntHandler(uint32_t uart_id);
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STATIC void UART0IntHandler(void);
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STATIC void UART1IntHandler(void);
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2015-09-22 22:20:29 +01:00
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STATIC void uart_irq_enable (mp_obj_t self_in);
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STATIC void uart_irq_disable (mp_obj_t self_in);
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2015-02-06 14:35:48 +00:00
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/******************************************************************************
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DEFINE PRIVATE TYPES
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******************************************************************************/
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struct _pyb_uart_obj_t {
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mp_obj_base_t base;
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2015-02-20 15:31:30 +00:00
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pyb_uart_id_t uart_id;
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2015-02-06 14:35:48 +00:00
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uint reg;
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uint baudrate;
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uint config;
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uint flowcontrol;
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byte *read_buf; // read buffer pointer
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volatile uint16_t read_buf_head; // indexes first empty slot
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uint16_t read_buf_tail; // indexes first full slot (not full if equals head)
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2015-03-26 09:25:28 +00:00
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byte peripheral;
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byte irq_trigger;
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2015-09-22 22:20:29 +01:00
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bool irq_enabled;
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byte irq_flags;
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2015-02-06 14:35:48 +00:00
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};
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2015-03-17 10:05:59 +00:00
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/******************************************************************************
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DECLARE PRIVATE DATA
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******************************************************************************/
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2015-09-07 08:23:46 +01:00
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STATIC pyb_uart_obj_t pyb_uart_obj[PYB_NUM_UARTS] = { {.reg = UARTA0_BASE, .baudrate = 0, .read_buf = NULL, .peripheral = PRCM_UARTA0},
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{.reg = UARTA1_BASE, .baudrate = 0, .read_buf = NULL, .peripheral = PRCM_UARTA1} };
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2015-09-22 22:20:29 +01:00
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STATIC const mp_irq_methods_t uart_irq_methods;
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2015-03-17 10:05:59 +00:00
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2015-09-08 14:07:42 +01:00
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STATIC const mp_obj_t pyb_uart_def_pin[PYB_NUM_UARTS][2] = { {&pin_GP1, &pin_GP2}, {&pin_GP3, &pin_GP4} };
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2015-09-07 08:23:46 +01:00
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2015-02-06 14:35:48 +00:00
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/******************************************************************************
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DEFINE PUBLIC FUNCTIONS
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******************************************************************************/
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void uart_init0 (void) {
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2015-09-07 08:23:46 +01:00
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// save references of the UART objects, to prevent the read buffers from being trashed by the gc
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MP_STATE_PORT(pyb_uart_objs)[0] = &pyb_uart_obj[0];
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MP_STATE_PORT(pyb_uart_objs)[1] = &pyb_uart_obj[1];
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2015-02-06 14:35:48 +00:00
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}
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2015-09-07 08:23:46 +01:00
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uint32_t uart_rx_any(pyb_uart_obj_t *self) {
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if (self->read_buf_tail != self->read_buf_head) {
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// buffering via irq
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return (self->read_buf_head > self->read_buf_tail) ? self->read_buf_head - self->read_buf_tail :
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PYBUART_RX_BUFFER_LEN - self->read_buf_tail + self->read_buf_head;
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}
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return MAP_UARTCharsAvail(self->reg) ? 1 : 0;
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2015-03-04 12:52:39 +00:00
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}
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int uart_rx_char(pyb_uart_obj_t *self) {
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if (self->read_buf_tail != self->read_buf_head) {
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2015-09-07 08:23:46 +01:00
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// buffering via irq
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2015-03-04 12:52:39 +00:00
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int data = self->read_buf[self->read_buf_tail];
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2015-09-07 08:23:46 +01:00
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self->read_buf_tail = (self->read_buf_tail + 1) % PYBUART_RX_BUFFER_LEN;
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2015-03-04 12:52:39 +00:00
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return data;
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} else {
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// no buffering
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return MAP_UARTCharGetNonBlocking(self->reg);
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}
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}
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bool uart_tx_char(pyb_uart_obj_t *self, int c) {
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uint32_t timeout = 0;
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while (!MAP_UARTCharPutNonBlocking(self->reg, c)) {
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2015-09-07 08:23:46 +01:00
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if (timeout++ > ((PYBUART_TX_MAX_TIMEOUT_MS * 1000) / PYBUART_TX_WAIT_US(self->baudrate))) {
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2015-03-04 12:52:39 +00:00
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return false;
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}
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2015-09-07 08:23:46 +01:00
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UtilsDelay(UTILS_DELAY_US_TO_COUNT(PYBUART_TX_WAIT_US(self->baudrate)));
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2015-03-04 12:52:39 +00:00
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}
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return true;
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}
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bool uart_tx_strn(pyb_uart_obj_t *self, const char *str, uint len) {
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for (const char *top = str + len; str < top; str++) {
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if (!uart_tx_char(self, *str)) {
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return false;
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}
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}
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return true;
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}
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/******************************************************************************
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DEFINE PRIVATE FUNCTIONS
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******************************************************************************/
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2015-02-20 15:31:30 +00:00
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// assumes init parameters have been set up correctly
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2015-03-04 12:52:39 +00:00
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STATIC void uart_init (pyb_uart_obj_t *self) {
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2015-02-06 14:35:48 +00:00
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// Enable the peripheral clock
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2015-03-26 09:25:28 +00:00
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MAP_PRCMPeripheralClkEnable(self->peripheral, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
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2015-02-06 14:35:48 +00:00
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// Reset the uart
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2015-03-26 09:25:28 +00:00
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MAP_PRCMPeripheralReset(self->peripheral);
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2015-02-06 14:35:48 +00:00
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2015-09-07 08:23:46 +01:00
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// re-allocate the read buffer after resetting the uart (which automatically disables any irqs)
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self->read_buf_head = 0;
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self->read_buf_tail = 0;
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self->read_buf = MP_OBJ_NULL; // free the read buffer before allocating again
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self->read_buf = m_new(byte, PYBUART_RX_BUFFER_LEN);
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2015-02-06 14:35:48 +00:00
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// Initialize the UART
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2015-03-26 09:25:28 +00:00
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MAP_UARTConfigSetExpClk(self->reg, MAP_PRCMPeripheralClockGet(self->peripheral),
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2015-02-06 14:35:48 +00:00
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self->baudrate, self->config);
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2015-03-26 09:25:28 +00:00
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// Enable the FIFO
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2015-02-06 14:35:48 +00:00
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MAP_UARTFIFOEnable(self->reg);
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// Configure the FIFO interrupt levels
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MAP_UARTFIFOLevelSet(self->reg, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
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2015-03-04 12:52:39 +00:00
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2015-02-06 14:35:48 +00:00
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// Configure the flow control mode
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UARTFlowControlSet(self->reg, self->flowcontrol);
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}
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2015-09-07 08:23:46 +01:00
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// Waits at most timeout microseconds for at least 1 char to become ready for
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2015-02-06 14:35:48 +00:00
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// reading (from buf or for direct reading).
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// Returns true if something available, false if not.
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2015-09-07 08:23:46 +01:00
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STATIC bool uart_rx_wait (pyb_uart_obj_t *self) {
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int timeout = PYBUART_RX_TIMEOUT_US(self->baudrate);
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2015-03-26 09:25:28 +00:00
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for ( ; ; ) {
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2015-02-06 14:35:48 +00:00
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if (uart_rx_any(self)) {
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2015-09-07 08:23:46 +01:00
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return true; // we have at least 1 char ready for reading
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2015-02-06 14:35:48 +00:00
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}
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if (timeout > 0) {
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2015-09-07 08:23:46 +01:00
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UtilsDelay(UTILS_DELAY_US_TO_COUNT(1));
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2015-02-06 14:35:48 +00:00
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timeout--;
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}
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else {
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return false;
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}
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}
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}
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2015-09-22 22:20:29 +01:00
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STATIC mp_obj_t uart_irq_new (pyb_uart_obj_t *self, byte trigger, mp_int_t priority, mp_obj_t handler) {
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// disable the uart interrupts before updating anything
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uart_irq_disable (self);
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if (self->uart_id == PYB_UART_0) {
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MAP_IntPrioritySet(INT_UARTA0, priority);
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MAP_UARTIntRegister(self->reg, UART0IntHandler);
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} else {
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MAP_IntPrioritySet(INT_UARTA1, priority);
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MAP_UARTIntRegister(self->reg, UART1IntHandler);
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}
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// create the callback
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mp_obj_t _irq = mp_irq_new ((mp_obj_t)self, handler, &uart_irq_methods);
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// enable the interrupts now
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self->irq_trigger = trigger;
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uart_irq_enable (self);
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return _irq;
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}
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2015-02-20 15:31:30 +00:00
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STATIC void UARTGenericIntHandler(uint32_t uart_id) {
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pyb_uart_obj_t *self;
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uint32_t status;
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2015-02-06 14:35:48 +00:00
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2015-03-17 10:05:59 +00:00
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self = &pyb_uart_obj[uart_id];
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status = MAP_UARTIntStatus(self->reg, true);
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// receive interrupt
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if (status & (UART_INT_RX | UART_INT_RT)) {
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2015-09-22 22:20:29 +01:00
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// set the flags
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self->irq_flags = UART_TRIGGER_RX_ANY;
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2015-03-17 10:05:59 +00:00
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MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
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while (UARTCharsAvail(self->reg)) {
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int data = MAP_UARTCharGetNonBlocking(self->reg);
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2017-09-04 08:32:14 +01:00
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if (MP_STATE_PORT(os_term_dup_obj) && MP_STATE_PORT(os_term_dup_obj)->stream_o == self && data == mp_interrupt_char) {
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2015-03-26 09:25:28 +00:00
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// raise an exception when interrupts are finished
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2021-04-28 01:57:34 +01:00
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mp_sched_keyboard_interrupt();
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2015-09-25 14:20:07 +01:00
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} else { // there's always a read buffer available
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2015-09-07 08:23:46 +01:00
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uint16_t next_head = (self->read_buf_head + 1) % PYBUART_RX_BUFFER_LEN;
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2015-03-17 10:05:59 +00:00
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if (next_head != self->read_buf_tail) {
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// only store data if room in buf
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self->read_buf[self->read_buf_head] = data;
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self->read_buf_head = next_head;
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2015-02-06 14:35:48 +00:00
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}
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}
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}
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2015-09-22 22:20:29 +01:00
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}
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2015-09-07 20:19:11 +01:00
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2015-09-22 22:20:29 +01:00
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// check the flags to see if the user handler should be called
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|
if ((self->irq_trigger & self->irq_flags) && self->irq_enabled) {
|
|
|
|
// call the user defined handler
|
|
|
|
mp_irq_handler(mp_irq_find(self));
|
2015-09-07 20:19:11 +01:00
|
|
|
}
|
2015-09-22 22:20:29 +01:00
|
|
|
|
|
|
|
// clear the flags
|
|
|
|
self->irq_flags = 0;
|
2015-09-07 20:19:11 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
STATIC void uart_check_init(pyb_uart_obj_t *self) {
|
|
|
|
// not initialized
|
|
|
|
if (!self->baudrate) {
|
2017-02-22 01:36:23 +00:00
|
|
|
mp_raise_OSError(MP_EPERM);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC void UART0IntHandler(void) {
|
|
|
|
UARTGenericIntHandler(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC void UART1IntHandler(void) {
|
|
|
|
UARTGenericIntHandler(1);
|
|
|
|
}
|
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
STATIC void uart_irq_enable (mp_obj_t self_in) {
|
2015-03-26 09:25:28 +00:00
|
|
|
pyb_uart_obj_t *self = self_in;
|
2015-09-07 08:23:46 +01:00
|
|
|
// check for any of the rx interrupt types
|
2015-09-22 22:20:29 +01:00
|
|
|
if (self->irq_trigger & (UART_TRIGGER_RX_ANY | UART_TRIGGER_RX_HALF | UART_TRIGGER_RX_FULL)) {
|
2015-09-07 08:23:46 +01:00
|
|
|
MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
|
|
|
|
MAP_UARTIntEnable(self->reg, UART_INT_RX | UART_INT_RT);
|
|
|
|
}
|
2015-09-22 22:20:29 +01:00
|
|
|
self->irq_enabled = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC void uart_irq_disable (mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
self->irq_enabled = false;
|
2015-03-26 09:25:28 +00:00
|
|
|
}
|
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
STATIC int uart_irq_flags (mp_obj_t self_in) {
|
2015-03-26 09:25:28 +00:00
|
|
|
pyb_uart_obj_t *self = self_in;
|
2015-09-22 22:20:29 +01:00
|
|
|
return self->irq_flags;
|
2015-03-26 09:25:28 +00:00
|
|
|
}
|
|
|
|
|
2015-02-06 14:35:48 +00:00
|
|
|
/******************************************************************************/
|
2017-06-30 08:22:17 +01:00
|
|
|
/* MicroPython bindings */
|
2015-02-06 14:35:48 +00:00
|
|
|
|
2015-04-09 23:56:15 +01:00
|
|
|
STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
|
2015-02-06 14:35:48 +00:00
|
|
|
pyb_uart_obj_t *self = self_in;
|
2015-03-26 09:25:28 +00:00
|
|
|
if (self->baudrate > 0) {
|
2015-09-07 08:23:46 +01:00
|
|
|
mp_printf(print, "UART(%u, baudrate=%u, bits=", self->uart_id, self->baudrate);
|
2015-02-06 14:35:48 +00:00
|
|
|
switch (self->config & UART_CONFIG_WLEN_MASK) {
|
|
|
|
case UART_CONFIG_WLEN_5:
|
2015-04-09 23:56:15 +01:00
|
|
|
mp_print_str(print, "5");
|
2015-02-06 14:35:48 +00:00
|
|
|
break;
|
|
|
|
case UART_CONFIG_WLEN_6:
|
2015-04-09 23:56:15 +01:00
|
|
|
mp_print_str(print, "6");
|
2015-02-06 14:35:48 +00:00
|
|
|
break;
|
|
|
|
case UART_CONFIG_WLEN_7:
|
2015-04-09 23:56:15 +01:00
|
|
|
mp_print_str(print, "7");
|
2015-02-06 14:35:48 +00:00
|
|
|
break;
|
|
|
|
case UART_CONFIG_WLEN_8:
|
2015-04-09 23:56:15 +01:00
|
|
|
mp_print_str(print, "8");
|
2015-02-06 14:35:48 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if ((self->config & UART_CONFIG_PAR_MASK) == UART_CONFIG_PAR_NONE) {
|
2015-04-09 23:56:15 +01:00
|
|
|
mp_print_str(print, ", parity=None");
|
2015-02-06 14:35:48 +00:00
|
|
|
} else {
|
2015-09-13 14:59:45 +01:00
|
|
|
mp_printf(print, ", parity=UART.%q", (self->config & UART_CONFIG_PAR_MASK) == UART_CONFIG_PAR_EVEN ? MP_QSTR_EVEN : MP_QSTR_ODD);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
2015-09-07 08:23:46 +01:00
|
|
|
mp_printf(print, ", stop=%u)", (self->config & UART_CONFIG_STOP_MASK) == UART_CONFIG_STOP_ONE ? 1 : 2);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
2015-03-26 09:25:28 +00:00
|
|
|
else {
|
2015-09-07 08:23:46 +01:00
|
|
|
mp_printf(print, "UART(%u)", self->uart_id);
|
2015-03-26 09:25:28 +00:00
|
|
|
}
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
|
2015-09-16 13:09:51 +01:00
|
|
|
STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, const mp_arg_val_t *args) {
|
2015-03-04 12:52:39 +00:00
|
|
|
// get the baudrate
|
2015-09-07 08:23:46 +01:00
|
|
|
if (args[0].u_int <= 0) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
uint baudrate = args[0].u_int;
|
|
|
|
uint config;
|
|
|
|
switch (args[1].u_int) {
|
|
|
|
case 5:
|
|
|
|
config = UART_CONFIG_WLEN_5;
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
config = UART_CONFIG_WLEN_6;
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
config = UART_CONFIG_WLEN_7;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
config = UART_CONFIG_WLEN_8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto error;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// parity
|
|
|
|
if (args[2].u_obj == mp_const_none) {
|
|
|
|
config |= UART_CONFIG_PAR_NONE;
|
|
|
|
} else {
|
2015-09-13 14:59:45 +01:00
|
|
|
uint parity = mp_obj_get_int(args[2].u_obj);
|
2017-04-08 22:17:29 +01:00
|
|
|
if (parity == 0) {
|
|
|
|
config |= UART_CONFIG_PAR_EVEN;
|
|
|
|
} else if (parity == 1) {
|
|
|
|
config |= UART_CONFIG_PAR_ODD;
|
|
|
|
} else {
|
2015-09-13 14:59:45 +01:00
|
|
|
goto error;
|
|
|
|
}
|
2015-09-07 08:23:46 +01:00
|
|
|
}
|
|
|
|
// stop bits
|
|
|
|
config |= (args[3].u_int == 1 ? UART_CONFIG_STOP_ONE : UART_CONFIG_STOP_TWO);
|
|
|
|
|
2015-09-08 14:07:42 +01:00
|
|
|
// assign the pins
|
2015-09-07 08:23:46 +01:00
|
|
|
mp_obj_t pins_o = args[4].u_obj;
|
|
|
|
uint flowcontrol = UART_FLOWCONTROL_NONE;
|
|
|
|
if (pins_o != mp_const_none) {
|
2015-09-08 14:07:42 +01:00
|
|
|
mp_obj_t *pins;
|
2017-03-26 07:17:49 +01:00
|
|
|
size_t n_pins = 2;
|
2015-09-07 08:23:46 +01:00
|
|
|
if (pins_o == MP_OBJ_NULL) {
|
|
|
|
// use the default pins
|
2015-09-08 14:07:42 +01:00
|
|
|
pins = (mp_obj_t *)pyb_uart_def_pin[self->uart_id];
|
2015-02-06 14:35:48 +00:00
|
|
|
} else {
|
2015-09-08 14:07:42 +01:00
|
|
|
mp_obj_get_array(pins_o, &n_pins, &pins);
|
2015-09-07 08:23:46 +01:00
|
|
|
if (n_pins != 2 && n_pins != 4) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
if (n_pins == 4) {
|
2015-09-08 14:07:42 +01:00
|
|
|
if (pins[PIN_TYPE_UART_RTS] != mp_const_none && pins[PIN_TYPE_UART_RX] == mp_const_none) {
|
2015-09-07 08:23:46 +01:00
|
|
|
goto error; // RTS pin given in TX only mode
|
2015-09-08 14:07:42 +01:00
|
|
|
} else if (pins[PIN_TYPE_UART_CTS] != mp_const_none && pins[PIN_TYPE_UART_TX] == mp_const_none) {
|
2015-09-07 08:23:46 +01:00
|
|
|
goto error; // CTS pin given in RX only mode
|
|
|
|
} else {
|
2015-09-08 14:07:42 +01:00
|
|
|
if (pins[PIN_TYPE_UART_RTS] != mp_const_none) {
|
2015-09-07 08:23:46 +01:00
|
|
|
flowcontrol |= UART_FLOWCONTROL_RX;
|
|
|
|
}
|
2015-09-08 14:07:42 +01:00
|
|
|
if (pins[PIN_TYPE_UART_CTS] != mp_const_none) {
|
2015-09-07 08:23:46 +01:00
|
|
|
flowcontrol |= UART_FLOWCONTROL_TX;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2015-06-09 15:15:23 +01:00
|
|
|
}
|
2015-09-08 14:07:42 +01:00
|
|
|
pin_assign_pins_af (pins, n_pins, PIN_TYPE_STD_PU, PIN_FN_UART, self->uart_id);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
2015-03-26 09:25:28 +00:00
|
|
|
|
2015-09-07 08:23:46 +01:00
|
|
|
self->baudrate = baudrate;
|
|
|
|
self->config = config;
|
|
|
|
self->flowcontrol = flowcontrol;
|
|
|
|
|
2015-03-04 12:52:39 +00:00
|
|
|
// initialize and enable the uart
|
|
|
|
uart_init (self);
|
|
|
|
// register it with the sleep module
|
2015-09-27 12:45:48 +01:00
|
|
|
pyb_sleep_add ((const mp_obj_t)self, (WakeUpCB_t)uart_init);
|
2015-09-07 20:19:11 +01:00
|
|
|
// enable the callback
|
2015-09-22 22:20:29 +01:00
|
|
|
uart_irq_new (self, UART_TRIGGER_RX_ANY, INT_PRIORITY_LVL_3, mp_const_none);
|
|
|
|
// disable the irq (from the user point of view)
|
|
|
|
uart_irq_disable(self);
|
2015-02-06 14:35:48 +00:00
|
|
|
|
|
|
|
return mp_const_none;
|
2015-06-09 15:15:23 +01:00
|
|
|
|
|
|
|
error:
|
2020-03-02 11:35:22 +00:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("invalid argument(s) value"));
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
|
2015-09-11 08:33:19 +01:00
|
|
|
STATIC const mp_arg_t pyb_uart_init_args[] = {
|
2015-09-26 21:55:24 +01:00
|
|
|
{ MP_QSTR_id, MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
|
2015-09-11 08:33:19 +01:00
|
|
|
{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = 9600} },
|
|
|
|
{ MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} },
|
|
|
|
{ MP_QSTR_parity, MP_ARG_OBJ, {.u_obj = mp_const_none} },
|
|
|
|
{ MP_QSTR_stop, MP_ARG_INT, {.u_int = 1} },
|
|
|
|
{ MP_QSTR_pins, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
|
|
|
|
};
|
2017-01-04 13:10:42 +00:00
|
|
|
STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
|
2015-09-11 08:33:19 +01:00
|
|
|
// parse args
|
|
|
|
mp_map_t kw_args;
|
|
|
|
mp_map_init_fixed_table(&kw_args, n_kw, all_args + n_args);
|
|
|
|
mp_arg_val_t args[MP_ARRAY_SIZE(pyb_uart_init_args)];
|
|
|
|
mp_arg_parse_all(n_args, all_args, &kw_args, MP_ARRAY_SIZE(args), pyb_uart_init_args, args);
|
2015-02-06 14:35:48 +00:00
|
|
|
|
2015-02-20 15:31:30 +00:00
|
|
|
// work out the uart id
|
2015-09-13 20:44:09 +01:00
|
|
|
uint uart_id;
|
2015-09-26 21:55:24 +01:00
|
|
|
if (args[0].u_obj == MP_OBJ_NULL) {
|
2015-09-11 08:33:19 +01:00
|
|
|
if (args[5].u_obj != MP_OBJ_NULL) {
|
|
|
|
mp_obj_t *pins;
|
2017-03-26 07:17:49 +01:00
|
|
|
size_t n_pins = 2;
|
2015-09-11 08:33:19 +01:00
|
|
|
mp_obj_get_array(args[5].u_obj, &n_pins, &pins);
|
|
|
|
// check the Tx pin (or the Rx if Tx is None)
|
|
|
|
if (pins[0] == mp_const_none) {
|
|
|
|
uart_id = pin_find_peripheral_unit(pins[1], PIN_FN_UART, PIN_TYPE_UART_RX);
|
|
|
|
} else {
|
|
|
|
uart_id = pin_find_peripheral_unit(pins[0], PIN_FN_UART, PIN_TYPE_UART_TX);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// default id
|
|
|
|
uart_id = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
uart_id = mp_obj_get_int(args[0].u_obj);
|
|
|
|
}
|
2015-02-06 14:35:48 +00:00
|
|
|
|
2015-09-13 20:44:09 +01:00
|
|
|
if (uart_id > PYB_UART_1) {
|
2017-02-22 01:36:23 +00:00
|
|
|
mp_raise_OSError(MP_ENODEV);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
|
2015-03-17 10:05:59 +00:00
|
|
|
// get the correct uart instance
|
|
|
|
pyb_uart_obj_t *self = &pyb_uart_obj[uart_id];
|
|
|
|
self->base.type = &pyb_uart_type;
|
|
|
|
self->uart_id = uart_id;
|
2015-05-09 16:46:16 +01:00
|
|
|
|
2015-09-11 08:33:19 +01:00
|
|
|
// start the peripheral
|
|
|
|
pyb_uart_init_helper(self, &args[1]);
|
2015-02-06 14:35:48 +00:00
|
|
|
|
|
|
|
return self;
|
|
|
|
}
|
|
|
|
|
2017-08-30 01:59:58 +01:00
|
|
|
STATIC mp_obj_t pyb_uart_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
2015-09-11 08:33:19 +01:00
|
|
|
// parse args
|
|
|
|
mp_arg_val_t args[MP_ARRAY_SIZE(pyb_uart_init_args) - 1];
|
|
|
|
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(args), &pyb_uart_init_args[1], args);
|
|
|
|
return pyb_uart_init_helper(pos_args[0], args);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_init_obj, 1, pyb_uart_init);
|
|
|
|
|
2015-05-09 16:46:16 +01:00
|
|
|
STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) {
|
2015-02-06 14:35:48 +00:00
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
|
2015-02-27 15:50:06 +00:00
|
|
|
// unregister it with the sleep module
|
2015-09-27 12:45:48 +01:00
|
|
|
pyb_sleep_remove (self);
|
2015-03-26 09:25:28 +00:00
|
|
|
// invalidate the baudrate
|
|
|
|
self->baudrate = 0;
|
2015-09-07 08:23:46 +01:00
|
|
|
// free the read buffer
|
|
|
|
m_del(byte, self->read_buf, PYBUART_RX_BUFFER_LEN);
|
2015-02-06 14:35:48 +00:00
|
|
|
MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT);
|
|
|
|
MAP_UARTDisable(self->reg);
|
2015-03-26 09:25:28 +00:00
|
|
|
MAP_PRCMPeripheralClkDisable(self->peripheral, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
|
2015-02-06 14:35:48 +00:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_deinit_obj, pyb_uart_deinit);
|
|
|
|
|
|
|
|
STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
2015-09-07 20:19:11 +01:00
|
|
|
uart_check_init(self);
|
2015-09-07 08:23:46 +01:00
|
|
|
return mp_obj_new_int(uart_rx_any(self));
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any);
|
|
|
|
|
2015-09-07 08:23:46 +01:00
|
|
|
STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
2015-09-07 20:19:11 +01:00
|
|
|
uart_check_init(self);
|
2015-09-07 08:23:46 +01:00
|
|
|
// send a break signal for at least 2 complete frames
|
|
|
|
MAP_UARTBreakCtl(self->reg, true);
|
|
|
|
UtilsDelay(UTILS_DELAY_US_TO_COUNT(PYBUART_2_FRAMES_TIME_US(self->baudrate)));
|
|
|
|
MAP_UARTBreakCtl(self->reg, false);
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak);
|
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
/// \method irq(trigger, priority, handler, wake)
|
2017-08-30 01:59:58 +01:00
|
|
|
STATIC mp_obj_t pyb_uart_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
2015-09-22 22:20:29 +01:00
|
|
|
mp_arg_val_t args[mp_irq_INIT_NUM_ARGS];
|
|
|
|
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, mp_irq_INIT_NUM_ARGS, mp_irq_init_args, args);
|
2015-03-26 09:25:28 +00:00
|
|
|
|
|
|
|
// check if any parameters were passed
|
|
|
|
pyb_uart_obj_t *self = pos_args[0];
|
2015-09-07 20:19:11 +01:00
|
|
|
uart_check_init(self);
|
2015-03-26 09:25:28 +00:00
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
// convert the priority to the correct value
|
|
|
|
uint priority = mp_irq_translate_priority (args[1].u_int);
|
2015-03-26 09:25:28 +00:00
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
// check the power mode
|
|
|
|
uint8_t pwrmode = (args[3].u_obj == mp_const_none) ? PYB_PWR_MODE_ACTIVE : mp_obj_get_int(args[3].u_obj);
|
|
|
|
if (PYB_PWR_MODE_ACTIVE != pwrmode) {
|
|
|
|
goto invalid_args;
|
|
|
|
}
|
2015-03-26 09:25:28 +00:00
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
// check the trigger
|
|
|
|
uint trigger = mp_obj_get_int(args[0].u_obj);
|
|
|
|
if (!trigger || trigger > (UART_TRIGGER_RX_ANY | UART_TRIGGER_RX_HALF | UART_TRIGGER_RX_FULL | UART_TRIGGER_TX_DONE)) {
|
|
|
|
goto invalid_args;
|
2015-03-26 09:25:28 +00:00
|
|
|
}
|
2015-09-22 22:20:29 +01:00
|
|
|
|
|
|
|
// register a new callback
|
|
|
|
return uart_irq_new (self, trigger, priority, args[2].u_obj);
|
|
|
|
|
|
|
|
invalid_args:
|
2020-03-02 11:35:22 +00:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("invalid argument(s) value"));
|
2015-03-26 09:25:28 +00:00
|
|
|
}
|
2015-10-14 11:32:01 +01:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_irq_obj, 1, pyb_uart_irq);
|
2015-03-26 09:25:28 +00:00
|
|
|
|
2022-08-26 17:08:29 +01:00
|
|
|
STATIC mp_obj_t machine_uart_txdone(mp_obj_t self_in) {
|
|
|
|
pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
|
|
|
|
|
|
|
if (MAP_UARTBusy(self->reg) == false) {
|
|
|
|
return mp_const_true;
|
|
|
|
} else {
|
|
|
|
return mp_const_false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_uart_txdone_obj, machine_uart_txdone);
|
|
|
|
|
2017-08-21 12:34:23 +01:00
|
|
|
STATIC const mp_rom_map_elem_t pyb_uart_locals_dict_table[] = {
|
2015-02-06 14:35:48 +00:00
|
|
|
// instance methods
|
2017-08-21 12:34:23 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_uart_init_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&pyb_uart_deinit_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_any), MP_ROM_PTR(&pyb_uart_any_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_sendbreak), MP_ROM_PTR(&pyb_uart_sendbreak_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&pyb_uart_irq_obj) },
|
2022-08-26 17:08:29 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_txdone), MP_ROM_PTR(&machine_uart_txdone_obj) },
|
2015-02-06 14:35:48 +00:00
|
|
|
|
|
|
|
/// \method read([nbytes])
|
2017-08-21 12:34:23 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_stream_read_obj) },
|
2015-02-06 14:35:48 +00:00
|
|
|
/// \method readline()
|
2017-08-21 12:34:23 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_readline), MP_ROM_PTR(&mp_stream_unbuffered_readline_obj) },
|
2015-02-06 14:35:48 +00:00
|
|
|
/// \method readinto(buf[, nbytes])
|
2017-08-21 12:34:23 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_stream_readinto_obj) },
|
2015-02-06 14:35:48 +00:00
|
|
|
/// \method write(buf)
|
2017-08-21 12:34:23 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_stream_write_obj) },
|
2022-08-26 17:08:29 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_flush), MP_ROM_PTR(&mp_stream_flush_obj) },
|
2015-02-06 14:35:48 +00:00
|
|
|
|
|
|
|
// class constants
|
2017-08-21 12:34:23 +01:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_RX_ANY), MP_ROM_INT(UART_TRIGGER_RX_ANY) },
|
2015-02-06 14:35:48 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table);
|
|
|
|
|
|
|
|
STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
byte *buf = buf_in;
|
2015-09-07 20:19:11 +01:00
|
|
|
uart_check_init(self);
|
2015-02-06 14:35:48 +00:00
|
|
|
|
|
|
|
// make sure we want at least 1 char
|
|
|
|
if (size == 0) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// wait for first char to become available
|
2015-09-07 08:23:46 +01:00
|
|
|
if (!uart_rx_wait(self)) {
|
2017-02-22 00:53:53 +00:00
|
|
|
// return MP_EAGAIN error to indicate non-blocking (then read() method returns None)
|
|
|
|
*errcode = MP_EAGAIN;
|
2015-10-20 08:27:21 +01:00
|
|
|
return MP_STREAM_ERROR;
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// read the data
|
|
|
|
byte *orig_buf = buf;
|
2015-03-26 09:25:28 +00:00
|
|
|
for ( ; ; ) {
|
2015-02-06 14:35:48 +00:00
|
|
|
*buf++ = uart_rx_char(self);
|
2015-09-07 08:23:46 +01:00
|
|
|
if (--size == 0 || !uart_rx_wait(self)) {
|
2015-02-06 14:35:48 +00:00
|
|
|
// return number of bytes read
|
|
|
|
return buf - orig_buf;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
const char *buf = buf_in;
|
2015-09-07 20:19:11 +01:00
|
|
|
uart_check_init(self);
|
2015-02-06 14:35:48 +00:00
|
|
|
|
|
|
|
// write the data
|
|
|
|
if (!uart_tx_strn(self, buf, size)) {
|
2017-02-22 01:36:23 +00:00
|
|
|
mp_raise_OSError(MP_EIO);
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC mp_uint_t pyb_uart_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
|
|
|
|
pyb_uart_obj_t *self = self_in;
|
|
|
|
mp_uint_t ret;
|
2015-09-07 20:19:11 +01:00
|
|
|
uart_check_init(self);
|
|
|
|
|
2016-12-02 05:37:29 +00:00
|
|
|
if (request == MP_STREAM_POLL) {
|
2015-02-06 14:35:48 +00:00
|
|
|
mp_uint_t flags = arg;
|
|
|
|
ret = 0;
|
2016-12-02 05:37:29 +00:00
|
|
|
if ((flags & MP_STREAM_POLL_RD) && uart_rx_any(self)) {
|
|
|
|
ret |= MP_STREAM_POLL_RD;
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
2016-12-02 05:37:29 +00:00
|
|
|
if ((flags & MP_STREAM_POLL_WR) && MAP_UARTSpaceAvail(self->reg)) {
|
|
|
|
ret |= MP_STREAM_POLL_WR;
|
2015-02-06 14:35:48 +00:00
|
|
|
}
|
2022-08-26 17:08:29 +01:00
|
|
|
} else if (request == MP_STREAM_FLUSH) {
|
|
|
|
// The timeout is estimated using the buffer size and the baudrate.
|
|
|
|
// Take the worst case assumptions at 13 bit symbol size times 2.
|
|
|
|
uint64_t timeout = mp_hal_ticks_ms() +
|
|
|
|
(PYBUART_TX_BUFFER_LEN) * 13000 * 2 / self->baudrate;
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (machine_uart_txdone((mp_obj_t)self) == mp_const_true) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
MICROPY_EVENT_POLL_HOOK
|
|
|
|
} while (mp_hal_ticks_ms() < timeout);
|
|
|
|
|
|
|
|
*errcode = MP_ETIMEDOUT;
|
|
|
|
ret = MP_STREAM_ERROR;;
|
2015-02-06 14:35:48 +00:00
|
|
|
} else {
|
2017-02-22 00:53:53 +00:00
|
|
|
*errcode = MP_EINVAL;
|
2015-02-06 14:35:48 +00:00
|
|
|
ret = MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC const mp_stream_p_t uart_stream_p = {
|
|
|
|
.read = pyb_uart_read,
|
|
|
|
.write = pyb_uart_write,
|
|
|
|
.ioctl = pyb_uart_ioctl,
|
|
|
|
.is_text = false,
|
|
|
|
};
|
|
|
|
|
2015-09-22 22:20:29 +01:00
|
|
|
STATIC const mp_irq_methods_t uart_irq_methods = {
|
|
|
|
.init = pyb_uart_irq,
|
|
|
|
.enable = uart_irq_enable,
|
|
|
|
.disable = uart_irq_disable,
|
|
|
|
.flags = uart_irq_flags
|
2015-03-26 09:25:28 +00:00
|
|
|
};
|
|
|
|
|
2021-07-14 05:38:38 +01:00
|
|
|
MP_DEFINE_CONST_OBJ_TYPE(
|
|
|
|
pyb_uart_type,
|
|
|
|
MP_QSTR_UART,
|
2022-09-16 14:57:38 +01:00
|
|
|
MP_TYPE_FLAG_ITER_IS_STREAM,
|
2022-09-16 15:31:23 +01:00
|
|
|
make_new, pyb_uart_make_new,
|
2021-07-14 05:38:38 +01:00
|
|
|
print, pyb_uart_print,
|
|
|
|
protocol, &uart_stream_p,
|
2022-06-24 07:27:46 +01:00
|
|
|
locals_dict, &pyb_uart_locals_dict
|
2021-07-14 05:38:38 +01:00
|
|
|
);
|
2022-07-01 20:28:58 +01:00
|
|
|
|
|
|
|
MP_REGISTER_ROOT_POINTER(struct _pyb_uart_obj_t *pyb_uart_objs[2]);
|