micropython/ports/stm32/boards/stm32g0b1_af.csv

Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,ADC
PortA,PA0,SPI2_SCK/I2S2_CK,USART2_CTS,TIM2_CH1/TIM2_ETR,,USART4_TX,LPTIM1_OUT,UCPD2_FRSTX,COMP1_OUT,,,,,,,,,ADC1_IN0
PortA,PA1,SPI1_SCK/I2S1_CK,USART2_RTS/USART2_DE/USART2_CK,TIM2_CH2,,USART4_RX,TIM15_CH1N,I2C1_SMBA,EVENTOUT,,,,,,,,,ADC1_IN1
PortA,PA2,SPI1_MOSI/I2S1_SD,USART2_TX,TIM2_CH3,,UCPD1_FRSTX,TIM15_CH1,LPUART1_TX,COMP2_OUT,,,,,,,,,ADC1_IN2
PortA,PA3,SPI2_MISO/I2S2_MCK,USART2_RX,TIM2_CH4,,UCPD2_FRSTX,TIM15_CH2,LPUART1_RX,EVENTOUT,,,,,,,,,ADC1_IN3
PortA,PA4,SPI1_NSS/I2S1_WS,SPI2_MOSI/I2S2_SD,USB_NOE,USART6_TX,TIM14_CH1,LPTIM2_OUT,UCPD2_FRSTX,EVENTOUT,,SPI3_NSS,,,,,,,ADC1_IN4
PortA,PA5,SPI1_SCK/I2S1_CK,CEC,TIM2_CH1/TIM2_ETR,USART6_RX,USART3_TX,LPTIM2_ETR,UCPD1_FRSTX,EVENTOUT,,,,,,,,,ADC1_IN5
PortA,PA6,SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,USART6_CTS,USART3_CTS,TIM16_CH1,LPUART1_CTS,COMP1_OUT,I2C2_SDA,I2C3_SDA,,,,,,,ADC1_IN6
PortA,PA7,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,USART6_RTS/USART6_DE/USART6_CK,TIM14_CH1,TIM17_CH1,UCPD1_FRSTX,COMP2_OUT,I2C2_SCL,I2C3_SCL,,,,,,,ADC1_IN7
PortA,PA8,MCO,SPI2_NSS/I2S2_WS,TIM1_CH1,,CRS1_SYNC,LPTIM2_OUT,,EVENTOUT,I2C2_SMBA,,,,,,,,
PortA,PA9,MCO,USART1_TX,TIM1_CH2,,SPI2_MISO/I2S2_MCK,TIM15_BKIN,I2C1_SCL,EVENTOUT,I2C2_SCL,,,,,,,,
PortA,PA10,SPI2_MOSI/I2S2_SD,USART1_RX,TIM1_CH3,MCO2,,TIM17_BKIN,I2C1_SDA,EVENTOUT,I2C2_SDA,,,,,,,,
PortA,PA11,SPI1_MISO/I2S1_MCK,USART1_CTS,TIM1_CH4,FDCAN1_RX,,TIM1_BKIN2,I2C2_SCL,COMP1_OUT,,,,,,,,,
PortA,PA12,SPI1_MOSI/I2S1_SD,USART1_RTS/USART1_DE/USART1_CK,TIM1_ETR,FDCAN1_TX,,I2S_CKIN,I2C2_SDA,COMP2_OUT,,,,,,,,,
PortA,PA13,SWDIO,IR_OUT,USB_NOE,,,,,EVENTOUT,,,LPUART2_RX,,,,,,
PortA,PA14,SWCLK,USART2_TX,,,,,,EVENTOUT,,,LPUART2_TX,,,,,,
PortA,PA15,SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1/TIM2_ETR,MCO2,USART4_RTS/USART4_DE/USART4_CK,USART3_RTS/USART3_DE/USART3_CK,USB_NOE,EVENTOUT,I2C2_SMBA,SPI3_NSS,,,,,,,
PortB,PB0,SPI1_NSS/I2S1_WS,TIM3_CH3,TIM1_CH2N,FDCAN2_RX,USART3_RX,LPTIM1_OUT,UCPD1_FRSTX,COMP1_OUT,USART5_TX,,LPUART2_CTS,,,,,,ADC1_IN8
PortB,PB1,TIM14_CH1,TIM3_CH4,TIM1_CH3N,FDCAN2_TX,USART3_RTS/USART3_DE/USART3_CK,LPTIM2_IN1,LPUART1_RTS/LPUART1_DE,COMP3_OUT,USART5_RX,,LPUART2_RTS/LPUART2_DE,,,,,,ADC1_IN9
PortB,PB2,,SPI2_MISO/I2S2_MCK,,MCO2,USART3_TX,LPTIM1_OUT,,EVENTOUT,,,,,,,,,ADC1_IN10
PortB,PB3,SPI1_SCK/I2S1_CK,TIM1_CH2,TIM2_CH2,USART5_TX,USART1_RTS/USART1_DE/USART1_CK,,I2C3_SCL,EVENTOUT,I2C2_SCL,SPI3_SCK,,,,,,,
PortB,PB4,SPI1_MISO/I2S1_MCK,TIM3_CH1,,USART5_RX,USART1_CTS,TIM17_BKIN,I2C3_SDA,EVENTOUT,I2C2_SDA,SPI3_MISO,,,,,,,
PortB,PB5,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,FDCAN2_RX,,LPTIM1_IN1,I2C1_SMBA,COMP2_OUT,USART5_RTS/USART5_DE/USART5_CK,SPI3_MOSI,,,,,,,
PortB,PB6,USART1_TX,TIM1_CH3,TIM16_CH1N,FDCAN2_TX,SPI2_MISO/I2S2_MCK,LPTIM1_ETR,I2C1_SCL,EVENTOUT,USART5_CTS,TIM4_CH1,LPUART2_TX,,,,,,
PortB,PB7,USART1_RX,SPI2_MOSI/I2S2_SD,TIM17_CH1N,,USART4_CTS,LPTIM1_IN2,I2C1_SDA,EVENTOUT,,TIM4_CH2,LPUART2_RX,,,,,,
PortB,PB8,CEC,SPI2_SCK/I2S2_CK,TIM16_CH1,FDCAN1_RX,USART3_TX,TIM15_BKIN,I2C1_SCL,EVENTOUT,USART6_TX,TIM4_CH3,,,,,,,
PortB,PB9,IR_OUT,UCPD2_FRSTX,TIM17_CH1,FDCAN1_TX,USART3_RX,SPI2_NSS/I2S2_WS,I2C1_SDA,EVENTOUT,USART6_RX,TIM4_CH4,,,,,,,
PortB,PB10,CEC,LPUART1_RX,TIM2_CH3,,USART3_TX,SPI2_SCK/I2S2_CK,I2C2_SCL,COMP1_OUT,,,,,,,,,ADC1_IN11
PortB,PB11,SPI2_MOSI/I2S2_SD,LPUART1_TX,TIM2_CH4,,USART3_RX,,I2C2_SDA,COMP2_OUT,,,,,,,,,
PortB,PB12,SPI2_NSS/I2S2_WS,LPUART1_RTS/LPUART1_DE,TIM1_BKIN,FDCAN2_RX,,TIM15_BKIN,UCPD2_FRSTX,EVENTOUT,I2C2_SMBA,,,,,,,,
PortB,PB13,SPI2_SCK/I2S2_CK,LPUART1_CTS,TIM1_CH1N,FDCAN2_TX,USART3_CTS,TIM15_CH1N,I2C2_SCL,EVENTOUT,,,,,,,,,
PortB,PB14,SPI2_MISO/I2S2_MCK,UCPD1_FRSTX,TIM1_CH2N,,USART3_RTS/USART3_DE/USART3_CK,TIM15_CH1,I2C2_SDA,EVENTOUT,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,
PortB,PB15,SPI2_MOSI/I2S2_SD,,TIM1_CH3N,,TIM15_CH1N,TIM15_CH2,,EVENTOUT,USART6_CTS,,,,,,,,
PortC,PC0,LPTIM1_IN1,LPUART1_RX,LPTIM2_IN1,LPUART2_TX,USART6_TX,,I2C3_SCL,COMP3_OUT,,,,,,,,,
PortC,PC1,LPTIM1_OUT,LPUART1_TX,TIM15_CH1,LPUART2_RX,USART6_RX,,I2C3_SDA,,,,,,,,,,
PortC,PC2,LPTIM1_IN2,SPI2_MISO/I2S2_MCK,TIM15_CH2,FDCAN2_RX,,,,COMP3_OUT,,,,,,,,,
PortC,PC3,LPTIM1_ETR,SPI2_MOSI/I2S2_SD,LPTIM2_ETR,FDCAN2_TX,,,,,,,,,,,,,
PortC,PC4,USART3_TX,USART1_TX,TIM2_CH1/TIM2_ETR,FDCAN1_RX,,,,,,,,,,,,,
PortC,PC5,USART3_RX,USART1_RX,TIM2_CH2,FDCAN1_TX,,,,,,,,,,,,,ADC1_IN18
PortC,PC6,UCPD1_FRSTX,TIM3_CH1,TIM2_CH3,LPUART2_TX,,,,,,,,,,,,,
PortC,PC7,UCPD2_FRSTX,TIM3_CH2,TIM2_CH4,LPUART2_RX,,,,,,,,,,,,,
PortC,PC8,UCPD2_FRSTX,TIM3_CH3,TIM1_CH1,LPUART2_CTS,,,,,,,,,,,,,
PortC,PC9,I2S_CKIN,TIM3_CH4,TIM1_CH2,LPUART2_RTS/LPUART2_DE,,,USB_NOE,,,,,,,,,,
PortC,PC10,USART3_TX,USART4_TX,TIM1_CH3,,SPI3_SCK,,,,,,,,,,,,
PortC,PC11,USART3_RX,USART4_RX,TIM1_CH4,,SPI3_MISO,,,,,,,,,,,,
PortC,PC12,LPTIM1_IN1,UCPD1_FRSTX,TIM14_CH1,USART5_TX,SPI3_MOSI,,,,,,,,,,,,
PortC,PC13,,,TIM1_BKIN,,,,,,,,,,,,,,
PortC,PC14,,,TIM1_BKIN2,,,,,,,,,,,,,,
PortC,PC15,OSC32_EN,OSC_EN,TIM15_BKIN,,,,,,,,,,,,,,
PortD,PD0,EVENTOUT,SPI2_NSS/I2S2_WS,TIM16_CH1,FDCAN1_RX,,,,,,,,,,,,,
PortD,PD1,EVENTOUT,SPI2_SCK/I2S2_CK,TIM17_CH1,FDCAN1_TX,,,,,,,,,,,,,
PortD,PD2,USART3_RTS/USART3_DE/USART3_CK,TIM3_ETR,TIM1_CH1N,USART5_RX,,,,,,,,,,,,,
PortD,PD3,USART2_CTS,SPI2_MISO/I2S2_MCK,TIM1_CH2N,USART5_TX,,,,,,,,,,,,,
PortD,PD4,USART2_RTS/USART2_DE/USART2_CK,SPI2_MOSI/I2S2_SD,TIM1_CH3N,USART5_RTS/USART5_DE/USART5_CK,,,,,,,,,,,,,
PortD,PD5,USART2_TX,SPI1_MISO/I2S1_MCK,TIM1_BKIN,USART5_CTS,,,,,,,,,,,,,
PortD,PD6,USART2_RX,SPI1_MOSI/I2S1_SD,LPTIM2_OUT,,,,,,,,,,,,,,
PortD,PD7,,,,MCO2,,,,,,,,,,,,,
PortD,PD8,USART3_TX,SPI1_SCK/I2S1_CK,LPTIM1_OUT,,,,,,,,,,,,,,
PortD,PD9,USART3_RX,SPI1_NSS/I2S1_WS,TIM1_BKIN2,,,,,,,,,,,,,,
PortD,PD10,MCO,,,,,,,,,,,,,,,,
PortD,PD11,USART3_CTS,LPTIM2_ETR,,,,,,,,,,,,,,,
PortD,PD12,USART3_RTS/USART3_DE/USART3_CK,LPTIM2_IN1,TIM4_CH1,FDCAN1_RX,,,,,,,,,,,,,
PortD,PD13,,LPTIM2_OUT,TIM4_CH2,FDCAN1_TX,,,,,,,,,,,,,
PortD,PD14,,LPUART2_CTS,TIM4_CH3,FDCAN2_RX,,,,,,,,,,,,,
PortD,PD15,CRS1_SYNC,LPUART2_RTS/LPUART2_DE,TIM4_CH4,FDCAN2_TX,,,,,,,,,,,,,
PortE,PE0,TIM16_CH1,EVENTOUT,TIM4_ETR,,,,,,,,,,,,,,
PortE,PE1,TIM17_CH1,EVENTOUT,,,,,,,,,,,,,,,
PortE,PE2,,TIM3_ETR,,,,,,,,,,,,,,,
PortE,PE3,,TIM3_CH1,,,,,,,,,,,,,,,
PortE,PE4,,TIM3_CH2,,,,,,,,,,,,,,,
PortE,PE5,,TIM3_CH3,,,,,,,,,,,,,,,
PortE,PE6,,TIM3_CH4,,,,,,,,,,,,,,,
PortE,PE7,,TIM1_ETR,,USART5_RTS/USART5_DE/USART5_CK,,,,,,,,,,,,,
PortE,PE8,USART4_TX,TIM1_CH1N,,,,,,,,,,,,,,,
PortE,PE9,USART4_RX,TIM1_CH1,,,,,,,,,,,,,,,
PortE,PE10,,TIM1_CH2N,,USART5_TX,,,,,,,,,,,,,
PortE,PE11,,TIM1_CH2,,USART5_RX,,,,,,,,,,,,,
PortE,PE12,SPI1_NSS/I2S1_WS,TIM1_CH3N,,,,,,,,,,,,,,,
PortE,PE13,SPI1_SCK/I2S1_CK,TIM1_CH3,,,,,,,,,,,,,,,
PortE,PE14,SPI1_MISO/I2S1_MCK,TIM1_CH4,TIM1_BK2,,,,,,,,,,,,,,
PortE,PE15,SPI1_MOSI/I2S1_SD,TIM1_BK,,,,,,,,,,,,,,,
PortF,PF0,CRS1_SYNC,EVENTOUT,TIM14_CH1,,,,,,,,,,,,,,
PortF,PF1,OSC_EN,EVENTOUT,TIM15_CH1N,,,,,,,,,,,,,,
PortF,PF2,MCO,LPUART2_TX,,LPUART2_RTS/LPUART2_DE,,,,,,,,,,,,,
PortF,PF3,,LPUART2_RX,,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,,,,,,
PortF,PF4,,LPUART1_TX,,,,,,,,,,,,,,,
PortF,PF5,,LPUART1_RX,,,,,,,,,,,,,,,
PortF,PF6,,LPUART1_RTS/LPUART1_DE,,,,,,,,,,,,,,,
PortF,PF7,,LPUART1_CTS,,USART5_CTS,,,,,,,,,,,,,
PortF,PF8,,,,,,,,,,,,,,,,,
PortF,PF9,,,,USART6_TX,,,,,,,,,,,,,
PortF,PF10,,,,USART6_RX,,,,,,,,,,,,,
PortF,PF11,,,,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,,,,,,
PortF,PF12,TIM15_CH1,,,USART6_CTS,,,,,,,,,,,,,
PortF,PF13,TIM15_CH2,,,,,,,,,,,,,,,,
stm32/boards/NUCLEO_G0B1RE: Add NUCLEO_G0B1RE board definition. This commit adds a board definition for NUCLEO_G0B1RE. This board has the REPL on UART2 which is connected to the on-board ST-link USB-UART. Signed-off-by: Asensio Lorenzo Sempere <asensio.aerospace@gmail.com> 2022-02-12 20:52:32 +00:00			`Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,`
			`,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,ADC`
			`PortA,PA0,SPI2_SCK/I2S2_CK,USART2_CTS,TIM2_CH1/TIM2_ETR,,USART4_TX,LPTIM1_OUT,UCPD2_FRSTX,COMP1_OUT,,,,,,,,,ADC1_IN0`
			`PortA,PA1,SPI1_SCK/I2S1_CK,USART2_RTS/USART2_DE/USART2_CK,TIM2_CH2,,USART4_RX,TIM15_CH1N,I2C1_SMBA,EVENTOUT,,,,,,,,,ADC1_IN1`
			`PortA,PA2,SPI1_MOSI/I2S1_SD,USART2_TX,TIM2_CH3,,UCPD1_FRSTX,TIM15_CH1,LPUART1_TX,COMP2_OUT,,,,,,,,,ADC1_IN2`
			`PortA,PA3,SPI2_MISO/I2S2_MCK,USART2_RX,TIM2_CH4,,UCPD2_FRSTX,TIM15_CH2,LPUART1_RX,EVENTOUT,,,,,,,,,ADC1_IN3`
			`PortA,PA4,SPI1_NSS/I2S1_WS,SPI2_MOSI/I2S2_SD,USB_NOE,USART6_TX,TIM14_CH1,LPTIM2_OUT,UCPD2_FRSTX,EVENTOUT,,SPI3_NSS,,,,,,,ADC1_IN4`
			`PortA,PA5,SPI1_SCK/I2S1_CK,CEC,TIM2_CH1/TIM2_ETR,USART6_RX,USART3_TX,LPTIM2_ETR,UCPD1_FRSTX,EVENTOUT,,,,,,,,,ADC1_IN5`
			`PortA,PA6,SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,USART6_CTS,USART3_CTS,TIM16_CH1,LPUART1_CTS,COMP1_OUT,I2C2_SDA,I2C3_SDA,,,,,,,ADC1_IN6`
			`PortA,PA7,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,USART6_RTS/USART6_DE/USART6_CK,TIM14_CH1,TIM17_CH1,UCPD1_FRSTX,COMP2_OUT,I2C2_SCL,I2C3_SCL,,,,,,,ADC1_IN7`
			`PortA,PA8,MCO,SPI2_NSS/I2S2_WS,TIM1_CH1,,CRS1_SYNC,LPTIM2_OUT,,EVENTOUT,I2C2_SMBA,,,,,,,,`
			`PortA,PA9,MCO,USART1_TX,TIM1_CH2,,SPI2_MISO/I2S2_MCK,TIM15_BKIN,I2C1_SCL,EVENTOUT,I2C2_SCL,,,,,,,,`
			`PortA,PA10,SPI2_MOSI/I2S2_SD,USART1_RX,TIM1_CH3,MCO2,,TIM17_BKIN,I2C1_SDA,EVENTOUT,I2C2_SDA,,,,,,,,`
			`PortA,PA11,SPI1_MISO/I2S1_MCK,USART1_CTS,TIM1_CH4,FDCAN1_RX,,TIM1_BKIN2,I2C2_SCL,COMP1_OUT,,,,,,,,,`
			`PortA,PA12,SPI1_MOSI/I2S1_SD,USART1_RTS/USART1_DE/USART1_CK,TIM1_ETR,FDCAN1_TX,,I2S_CKIN,I2C2_SDA,COMP2_OUT,,,,,,,,,`
			`PortA,PA13,SWDIO,IR_OUT,USB_NOE,,,,,EVENTOUT,,,LPUART2_RX,,,,,,`
			`PortA,PA14,SWCLK,USART2_TX,,,,,,EVENTOUT,,,LPUART2_TX,,,,,,`
			`PortA,PA15,SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1/TIM2_ETR,MCO2,USART4_RTS/USART4_DE/USART4_CK,USART3_RTS/USART3_DE/USART3_CK,USB_NOE,EVENTOUT,I2C2_SMBA,SPI3_NSS,,,,,,,`
			`PortB,PB0,SPI1_NSS/I2S1_WS,TIM3_CH3,TIM1_CH2N,FDCAN2_RX,USART3_RX,LPTIM1_OUT,UCPD1_FRSTX,COMP1_OUT,USART5_TX,,LPUART2_CTS,,,,,,ADC1_IN8`
			`PortB,PB1,TIM14_CH1,TIM3_CH4,TIM1_CH3N,FDCAN2_TX,USART3_RTS/USART3_DE/USART3_CK,LPTIM2_IN1,LPUART1_RTS/LPUART1_DE,COMP3_OUT,USART5_RX,,LPUART2_RTS/LPUART2_DE,,,,,,ADC1_IN9`
			`PortB,PB2,,SPI2_MISO/I2S2_MCK,,MCO2,USART3_TX,LPTIM1_OUT,,EVENTOUT,,,,,,,,,ADC1_IN10`
			`PortB,PB3,SPI1_SCK/I2S1_CK,TIM1_CH2,TIM2_CH2,USART5_TX,USART1_RTS/USART1_DE/USART1_CK,,I2C3_SCL,EVENTOUT,I2C2_SCL,SPI3_SCK,,,,,,,`
			`PortB,PB4,SPI1_MISO/I2S1_MCK,TIM3_CH1,,USART5_RX,USART1_CTS,TIM17_BKIN,I2C3_SDA,EVENTOUT,I2C2_SDA,SPI3_MISO,,,,,,,`
			`PortB,PB5,SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,FDCAN2_RX,,LPTIM1_IN1,I2C1_SMBA,COMP2_OUT,USART5_RTS/USART5_DE/USART5_CK,SPI3_MOSI,,,,,,,`
			`PortB,PB6,USART1_TX,TIM1_CH3,TIM16_CH1N,FDCAN2_TX,SPI2_MISO/I2S2_MCK,LPTIM1_ETR,I2C1_SCL,EVENTOUT,USART5_CTS,TIM4_CH1,LPUART2_TX,,,,,,`
			`PortB,PB7,USART1_RX,SPI2_MOSI/I2S2_SD,TIM17_CH1N,,USART4_CTS,LPTIM1_IN2,I2C1_SDA,EVENTOUT,,TIM4_CH2,LPUART2_RX,,,,,,`
			`PortB,PB8,CEC,SPI2_SCK/I2S2_CK,TIM16_CH1,FDCAN1_RX,USART3_TX,TIM15_BKIN,I2C1_SCL,EVENTOUT,USART6_TX,TIM4_CH3,,,,,,,`
			`PortB,PB9,IR_OUT,UCPD2_FRSTX,TIM17_CH1,FDCAN1_TX,USART3_RX,SPI2_NSS/I2S2_WS,I2C1_SDA,EVENTOUT,USART6_RX,TIM4_CH4,,,,,,,`
			`PortB,PB10,CEC,LPUART1_RX,TIM2_CH3,,USART3_TX,SPI2_SCK/I2S2_CK,I2C2_SCL,COMP1_OUT,,,,,,,,,ADC1_IN11`
			`PortB,PB11,SPI2_MOSI/I2S2_SD,LPUART1_TX,TIM2_CH4,,USART3_RX,,I2C2_SDA,COMP2_OUT,,,,,,,,,`
			`PortB,PB12,SPI2_NSS/I2S2_WS,LPUART1_RTS/LPUART1_DE,TIM1_BKIN,FDCAN2_RX,,TIM15_BKIN,UCPD2_FRSTX,EVENTOUT,I2C2_SMBA,,,,,,,,`
			`PortB,PB13,SPI2_SCK/I2S2_CK,LPUART1_CTS,TIM1_CH1N,FDCAN2_TX,USART3_CTS,TIM15_CH1N,I2C2_SCL,EVENTOUT,,,,,,,,,`
			`PortB,PB14,SPI2_MISO/I2S2_MCK,UCPD1_FRSTX,TIM1_CH2N,,USART3_RTS/USART3_DE/USART3_CK,TIM15_CH1,I2C2_SDA,EVENTOUT,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,`
			`PortB,PB15,SPI2_MOSI/I2S2_SD,,TIM1_CH3N,,TIM15_CH1N,TIM15_CH2,,EVENTOUT,USART6_CTS,,,,,,,,`
			`PortC,PC0,LPTIM1_IN1,LPUART1_RX,LPTIM2_IN1,LPUART2_TX,USART6_TX,,I2C3_SCL,COMP3_OUT,,,,,,,,,`
			`PortC,PC1,LPTIM1_OUT,LPUART1_TX,TIM15_CH1,LPUART2_RX,USART6_RX,,I2C3_SDA,,,,,,,,,,`
			`PortC,PC2,LPTIM1_IN2,SPI2_MISO/I2S2_MCK,TIM15_CH2,FDCAN2_RX,,,,COMP3_OUT,,,,,,,,,`
			`PortC,PC3,LPTIM1_ETR,SPI2_MOSI/I2S2_SD,LPTIM2_ETR,FDCAN2_TX,,,,,,,,,,,,,`
			`PortC,PC4,USART3_TX,USART1_TX,TIM2_CH1/TIM2_ETR,FDCAN1_RX,,,,,,,,,,,,,`
			`PortC,PC5,USART3_RX,USART1_RX,TIM2_CH2,FDCAN1_TX,,,,,,,,,,,,,ADC1_IN18`
			`PortC,PC6,UCPD1_FRSTX,TIM3_CH1,TIM2_CH3,LPUART2_TX,,,,,,,,,,,,,`
			`PortC,PC7,UCPD2_FRSTX,TIM3_CH2,TIM2_CH4,LPUART2_RX,,,,,,,,,,,,,`
			`PortC,PC8,UCPD2_FRSTX,TIM3_CH3,TIM1_CH1,LPUART2_CTS,,,,,,,,,,,,,`
			`PortC,PC9,I2S_CKIN,TIM3_CH4,TIM1_CH2,LPUART2_RTS/LPUART2_DE,,,USB_NOE,,,,,,,,,,`
			`PortC,PC10,USART3_TX,USART4_TX,TIM1_CH3,,SPI3_SCK,,,,,,,,,,,,`
			`PortC,PC11,USART3_RX,USART4_RX,TIM1_CH4,,SPI3_MISO,,,,,,,,,,,,`
			`PortC,PC12,LPTIM1_IN1,UCPD1_FRSTX,TIM14_CH1,USART5_TX,SPI3_MOSI,,,,,,,,,,,,`
			`PortC,PC13,,,TIM1_BKIN,,,,,,,,,,,,,,`
			`PortC,PC14,,,TIM1_BKIN2,,,,,,,,,,,,,,`
			`PortC,PC15,OSC32_EN,OSC_EN,TIM15_BKIN,,,,,,,,,,,,,,`
			`PortD,PD0,EVENTOUT,SPI2_NSS/I2S2_WS,TIM16_CH1,FDCAN1_RX,,,,,,,,,,,,,`
			`PortD,PD1,EVENTOUT,SPI2_SCK/I2S2_CK,TIM17_CH1,FDCAN1_TX,,,,,,,,,,,,,`
			`PortD,PD2,USART3_RTS/USART3_DE/USART3_CK,TIM3_ETR,TIM1_CH1N,USART5_RX,,,,,,,,,,,,,`
			`PortD,PD3,USART2_CTS,SPI2_MISO/I2S2_MCK,TIM1_CH2N,USART5_TX,,,,,,,,,,,,,`
			`PortD,PD4,USART2_RTS/USART2_DE/USART2_CK,SPI2_MOSI/I2S2_SD,TIM1_CH3N,USART5_RTS/USART5_DE/USART5_CK,,,,,,,,,,,,,`
			`PortD,PD5,USART2_TX,SPI1_MISO/I2S1_MCK,TIM1_BKIN,USART5_CTS,,,,,,,,,,,,,`
			`PortD,PD6,USART2_RX,SPI1_MOSI/I2S1_SD,LPTIM2_OUT,,,,,,,,,,,,,,`
			`PortD,PD7,,,,MCO2,,,,,,,,,,,,,`
			`PortD,PD8,USART3_TX,SPI1_SCK/I2S1_CK,LPTIM1_OUT,,,,,,,,,,,,,,`
			`PortD,PD9,USART3_RX,SPI1_NSS/I2S1_WS,TIM1_BKIN2,,,,,,,,,,,,,,`
			`PortD,PD10,MCO,,,,,,,,,,,,,,,,`
			`PortD,PD11,USART3_CTS,LPTIM2_ETR,,,,,,,,,,,,,,,`
			`PortD,PD12,USART3_RTS/USART3_DE/USART3_CK,LPTIM2_IN1,TIM4_CH1,FDCAN1_RX,,,,,,,,,,,,,`
			`PortD,PD13,,LPTIM2_OUT,TIM4_CH2,FDCAN1_TX,,,,,,,,,,,,,`
			`PortD,PD14,,LPUART2_CTS,TIM4_CH3,FDCAN2_RX,,,,,,,,,,,,,`
			`PortD,PD15,CRS1_SYNC,LPUART2_RTS/LPUART2_DE,TIM4_CH4,FDCAN2_TX,,,,,,,,,,,,,`
			`PortE,PE0,TIM16_CH1,EVENTOUT,TIM4_ETR,,,,,,,,,,,,,,`
			`PortE,PE1,TIM17_CH1,EVENTOUT,,,,,,,,,,,,,,,`
			`PortE,PE2,,TIM3_ETR,,,,,,,,,,,,,,,`
			`PortE,PE3,,TIM3_CH1,,,,,,,,,,,,,,,`
			`PortE,PE4,,TIM3_CH2,,,,,,,,,,,,,,,`
			`PortE,PE5,,TIM3_CH3,,,,,,,,,,,,,,,`
			`PortE,PE6,,TIM3_CH4,,,,,,,,,,,,,,,`
			`PortE,PE7,,TIM1_ETR,,USART5_RTS/USART5_DE/USART5_CK,,,,,,,,,,,,,`
			`PortE,PE8,USART4_TX,TIM1_CH1N,,,,,,,,,,,,,,,`
			`PortE,PE9,USART4_RX,TIM1_CH1,,,,,,,,,,,,,,,`
			`PortE,PE10,,TIM1_CH2N,,USART5_TX,,,,,,,,,,,,,`
			`PortE,PE11,,TIM1_CH2,,USART5_RX,,,,,,,,,,,,,`
			`PortE,PE12,SPI1_NSS/I2S1_WS,TIM1_CH3N,,,,,,,,,,,,,,,`
			`PortE,PE13,SPI1_SCK/I2S1_CK,TIM1_CH3,,,,,,,,,,,,,,,`
			`PortE,PE14,SPI1_MISO/I2S1_MCK,TIM1_CH4,TIM1_BK2,,,,,,,,,,,,,,`
			`PortE,PE15,SPI1_MOSI/I2S1_SD,TIM1_BK,,,,,,,,,,,,,,,`
			`PortF,PF0,CRS1_SYNC,EVENTOUT,TIM14_CH1,,,,,,,,,,,,,,`
			`PortF,PF1,OSC_EN,EVENTOUT,TIM15_CH1N,,,,,,,,,,,,,,`
			`PortF,PF2,MCO,LPUART2_TX,,LPUART2_RTS/LPUART2_DE,,,,,,,,,,,,,`
			`PortF,PF3,,LPUART2_RX,,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,,,,,,`
			`PortF,PF4,,LPUART1_TX,,,,,,,,,,,,,,,`
			`PortF,PF5,,LPUART1_RX,,,,,,,,,,,,,,,`
			`PortF,PF6,,LPUART1_RTS/LPUART1_DE,,,,,,,,,,,,,,,`
			`PortF,PF7,,LPUART1_CTS,,USART5_CTS,,,,,,,,,,,,,`
			`PortF,PF8,,,,,,,,,,,,,,,,,`
			`PortF,PF9,,,,USART6_TX,,,,,,,,,,,,,`
			`PortF,PF10,,,,USART6_RX,,,,,,,,,,,,,`
			`PortF,PF11,,,,USART6_RTS/USART6_DE/USART6_CK,,,,,,,,,,,,,`
			`PortF,PF12,TIM15_CH1,,,USART6_CTS,,,,,,,,,,,,,`
			`PortF,PF13,TIM15_CH2,,,,,,,,,,,,,,,,`