2022-04-29 02:49:44 +01:00
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021,2022 Renesas Electronics Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdint.h>
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#include "hal_data.h"
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#include "ra_config.h"
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#include "ra_gpio.h"
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void ra_gpio_config(uint32_t pin, uint32_t mode, uint32_t pull, uint32_t drive, uint32_t alt) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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pwpr_unprotect();
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2022-06-23 14:27:47 +01:00
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_PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK | NCODR_MASK | PCR_MASK | PDR_MASK | DSCR1_MASK | DSCR_MASK);
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2022-04-29 02:49:44 +01:00
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switch (mode) {
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case GPIO_MODE_INPUT:
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2022-06-23 14:27:47 +01:00
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if (pull == GPIO_PULLUP) {
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2022-04-29 02:49:44 +01:00
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_PXXPFS(port, bit) |= PCR_MASK; // set pullup
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}
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break;
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case GPIO_MODE_OUTPUT_PP:
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_PXXPFS(port, bit) |= PDR_MASK; // output
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break;
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case GPIO_MODE_OUTPUT_OD:
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_PXXPFS(port, bit) |= (PDR_MASK | NCODR_MASK);
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break;
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case GPIO_MODE_AF_PP:
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_PXXPFS(port, bit) |= (PMR_MASK | PDR_MASK);
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break;
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case GPIO_MODE_AF_OD:
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_PXXPFS(port, bit) |= (PMR_MASK | PDR_MASK | NCODR_MASK);
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break;
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2022-06-23 14:27:47 +01:00
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case GPIO_MODE_ANALOG:
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_PXXPFS(port, bit) |= ASEL_MASK;
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break;
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2022-04-29 02:49:44 +01:00
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}
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switch (drive) {
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case GPIO_HIGH_POWER:
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_PXXPFS(port, bit) |= (DSCR1_MASK | DSCR_MASK);
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break;
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2022-06-23 14:27:47 +01:00
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case GPIO_MID_FAST_POWER:
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_PXXPFS(port, bit) |= DSCR1_MASK;
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break;
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case GPIO_MID_POWER:
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2022-04-29 02:49:44 +01:00
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_PXXPFS(port, bit) |= DSCR_MASK;
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break;
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case GPIO_LOW_POWER:
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2022-06-23 14:27:47 +01:00
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default:
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/* Bits are already cleared */
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2022-04-29 02:49:44 +01:00
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break;
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}
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_PXXPFS(port, bit) &= ~(uint32_t)(0x1f000000);
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if (alt != 0) {
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_PXXPFS(port, bit) |= (alt << 24); // Must set PSEL when PMR is 0
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_PXXPFS(port, bit) |= PMR_MASK;
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}
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pwpr_protect();
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}
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void ra_gpio_mode_output(uint32_t pin) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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pwpr_unprotect();
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_PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK | PCR_MASK); // GPIO
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_PXXPFS(port, bit) |= PDR_MASK; // output
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pwpr_protect();
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}
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void ra_gpio_mode_input(uint32_t pin) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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pwpr_unprotect();
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_PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO
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_PXXPFS(port, bit) &= ~PDR_MASK; // input
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pwpr_protect();
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}
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void ra_gpio_toggle(uint32_t pin) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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pwpr_unprotect();
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_PXXPFS(port, bit) ^= 1;
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pwpr_protect();
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}
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void ra_gpio_write(uint32_t pin, uint32_t value) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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pwpr_unprotect();
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if (value != 0) {
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_PXXPFS(port, bit) |= 1;
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} else {
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_PXXPFS(port, bit) &= ~(uint32_t)1;
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}
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pwpr_protect();
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}
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uint32_t ra_gpio_read(uint32_t pin) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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2022-06-23 14:27:47 +01:00
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return ((_PXXPFS(port, bit) & PIDR_MASK) != 0) ? 1 : 0;
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2022-04-29 02:49:44 +01:00
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}
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uint32_t ra_gpio_get_mode(uint32_t pin) {
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uint8_t mode = 0;
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2022-06-23 14:27:47 +01:00
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uint32_t pfs = _PXXPFS(GPIO_PORT(pin), GPIO_BIT(pin));
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if ((pfs & ASEL_MASK) != 0) {
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mode = GPIO_MODE_ANALOG;
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} else if ((pfs & PMR_MASK) != 0) {
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if ((pfs & NCODR_MASK) != 0) {
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mode = GPIO_MODE_AF_OD;
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} else {
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mode = GPIO_MODE_AF_PP;
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}
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} else if ((pfs & PDR_MASK) != 0) {
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if ((pfs & NCODR_MASK) != 0) {
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mode = GPIO_MODE_OUTPUT_OD;
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} else {
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mode = GPIO_MODE_OUTPUT_PP;
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}
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2022-04-29 02:49:44 +01:00
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} else {
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mode = GPIO_MODE_INPUT;
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}
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return mode;
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}
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uint32_t ra_gpio_get_pull(uint32_t pin) {
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uint8_t pull = 0;
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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2022-06-23 14:27:47 +01:00
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if ((_PXXPFS(port, bit) & PCR_MASK) != 0) {
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2022-04-29 02:49:44 +01:00
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pull = GPIO_PULLUP;
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} else {
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pull = GPIO_NOPULL;
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}
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return pull;
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}
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uint32_t ra_gpio_get_af(uint32_t pin) {
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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2022-06-23 14:27:47 +01:00
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return (_PXXPFS(port, bit) & PMR_MASK) != 0;
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2022-04-29 02:49:44 +01:00
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}
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uint32_t ra_gpio_get_drive(uint32_t pin) {
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uint8_t drive = 0;
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uint32_t port = GPIO_PORT(pin);
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uint32_t bit = GPIO_BIT(pin);
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2022-06-23 14:27:47 +01:00
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switch (_PXXPFS(port, bit) & (DSCR1_MASK | DSCR_MASK)) {
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2022-04-29 02:49:44 +01:00
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case (DSCR1_MASK | DSCR_MASK):
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drive = GPIO_HIGH_POWER;
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break;
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2022-06-23 14:27:47 +01:00
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case DSCR1_MASK:
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drive = GPIO_MID_FAST_POWER;
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break;
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2022-04-29 02:49:44 +01:00
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case DSCR_MASK:
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2022-06-23 14:27:47 +01:00
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drive = GPIO_MID_POWER;
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2022-04-29 02:49:44 +01:00
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break;
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case 0:
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default:
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drive = GPIO_LOW_POWER;
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break;
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}
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return drive;
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}
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