2020-01-20 11:25:51 +00:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// Options controlling how MicroPython is built, overriding defaults in py/mpconfig.h
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// Board specific definitions
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#include "mpconfigboard.h"
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2021-05-26 12:19:38 +01:00
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#include "fsl_common.h"
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2021-10-20 20:24:20 +01:00
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#include "lib/nxp_driver/sdk/CMSIS/Include/core_cm7.h"
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2020-01-20 11:25:51 +00:00
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2021-06-06 07:11:20 +01:00
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uint32_t trng_random_u32(void);
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2021-10-20 20:24:20 +01:00
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// Config level
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#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_FULL_FEATURES)
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2020-01-20 11:25:51 +00:00
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// Memory allocation policies
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2023-01-12 21:02:26 +00:00
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#if MICROPY_HW_SDRAM_AVAIL
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#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t
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#else
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2020-01-20 11:25:51 +00:00
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#define MICROPY_GC_STACK_ENTRY_TYPE uint16_t
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2023-01-12 21:02:26 +00:00
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#endif
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2020-01-20 11:25:51 +00:00
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#define MICROPY_ALLOC_PARSE_CHUNK_INIT (32)
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#define MICROPY_ALLOC_PATH_MAX (256)
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2021-05-26 12:19:38 +01:00
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// MicroPython emitters
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#define MICROPY_PERSISTENT_CODE_LOAD (1)
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#define MICROPY_EMIT_THUMB (1)
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#define MICROPY_EMIT_INLINE_THUMB (1)
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2021-09-17 07:25:33 +01:00
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// Optimisations
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2020-01-20 11:25:51 +00:00
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// Python internal features
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2022-05-04 03:24:43 +01:00
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#define MICROPY_TRACKED_ALLOC (MICROPY_SSL_MBEDTLS)
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2021-05-07 14:21:09 +01:00
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#define MICROPY_READER_VFS (1)
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2020-01-20 11:25:51 +00:00
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#define MICROPY_ENABLE_GC (1)
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2021-05-07 14:21:09 +01:00
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#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1)
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2020-01-20 11:25:51 +00:00
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#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ)
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2021-05-18 16:27:00 +01:00
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#define MICROPY_SCHEDULER_DEPTH (8)
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2021-05-07 14:21:09 +01:00
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#define MICROPY_VFS (1)
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2020-01-20 11:25:51 +00:00
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// Control over Python builtins
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2021-05-06 19:35:33 +01:00
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#define MICROPY_PY_BUILTINS_HELP_TEXT mimxrt_help_text
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2021-05-07 14:21:09 +01:00
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#define MICROPY_PY_SYS_PLATFORM "mimxrt"
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2020-01-20 11:25:51 +00:00
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// Extended modules
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2021-05-26 12:19:38 +01:00
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#define MICROPY_EPOCH_IS_1970 (1)
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2022-08-18 06:01:26 +01:00
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#define MICROPY_PY_SSL_FINALISER (MICROPY_PY_SSL)
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#define MICROPY_PY_TIME_GMTIME_LOCALTIME_MKTIME (1)
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#define MICROPY_PY_TIME_TIME_TIME_NS (1)
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2022-08-18 07:24:27 +01:00
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#define MICROPY_PY_TIME_INCLUDEFILE "ports/mimxrt/modtime.c"
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#define MICROPY_PY_OS_INCLUDEFILE "ports/mimxrt/modos.c"
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2021-07-03 17:39:17 +01:00
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#define MICROPY_PY_OS_DUPTERM (3)
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2022-08-18 06:01:26 +01:00
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#define MICROPY_PY_OS_DUPTERM_NOTIFY (1)
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#define MICROPY_PY_OS_SYNC (1)
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#define MICROPY_PY_OS_UNAME (1)
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#define MICROPY_PY_OS_URANDOM (1)
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#define MICROPY_PY_RANDOM_SEED_INIT_FUNC (trng_random_u32())
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2020-01-20 11:25:51 +00:00
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#define MICROPY_PY_MACHINE (1)
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2021-05-26 12:19:38 +01:00
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#define MICROPY_PY_MACHINE_PIN_MAKE_NEW mp_pin_make_new
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2021-08-19 21:00:38 +01:00
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#define MICROPY_PY_MACHINE_BITSTREAM (1)
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2021-06-19 09:51:45 +01:00
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#define MICROPY_PY_MACHINE_PULSE (1)
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mimxrt: Support PWM using the FLEXPWM and QTMR modules.
Frequency range 15Hz/18Hz to > 1 MHz, with decreasing resolution of the
duty cycle. The basic API is supported as documentated, except that
keyword parameters are accepted for both the instatiaton and the
PWM.init() call.
Extensions: support PWM for channel pairs. Channel pairs are declared by
supplying 2-element tuples for the pins. The two channels of a pair must
be the A/B channel of a FLEXPWM module. These form than a complementary
pair.
Additional supported keyword arguments:
- center=value Defines the center position of a pulse within the pulse
cycle. The align keyword is actually shortcut for center.
- sync=True|False: If set to True, the channels will be synchronized to a
submodule 0 channel, which has already to be enabled.
- align=PWM.MIDDLE | PMW.BEGIN | PWM.END. It defines, whether synchronized
channels are Center-Aligned or Edge-aligned. The channels must be either
complementary a channel pair or a group of synchronized channels. It may
as well be applied to a single channel, but withiout any benefit.
- invert= 0..3. Controls ouput inversion of the pins. Bit 0 controls the
first pin, bit 1 the second.
- deadtime=time_ns time of complementary channels for delaying the rising
slope.
- xor=0|1|2 xor causes the output of channel A and B to be xored. If
applied to a X channel, it shows the value oif A ^ B. If applied to an A
or B channel, both channel show the xored signal for xor=1. For xor=2,
the xored signal is split between channels A and B. See also the
Reference Manual, chapter about double pulses. The behavior of xor=2 can
also be achieved using the center method for locating a pulse within a
clock period.
The output is enabled for board pins only.
CPU pins may still be used for FLEXPWM, e.g. as sync source, but the signal
will not be routed to the output. That applies only to FLEXPWM pins. The
use of QTMR pins which are not board pins will be rejected.
As part of this commit, the _WFE() statement is removed from
ticks_delay_us64() to prevent PWM glitching during calls to sleep().
2021-07-26 11:48:25 +01:00
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#define MICROPY_PY_MACHINE_PWM (1)
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#define MICROPY_PY_MACHINE_PWM_INCLUDEFILE "ports/mimxrt/machine_pwm.c"
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2021-05-26 12:19:38 +01:00
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#define MICROPY_PY_MACHINE_I2C (1)
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2021-11-29 17:50:34 +00:00
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#ifndef MICROPY_PY_MACHINE_I2S
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#define MICROPY_PY_MACHINE_I2S (0)
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#endif
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2021-09-02 03:37:00 +01:00
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#define MICROPY_PY_MACHINE_SOFTI2C (1)
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2021-05-26 12:19:38 +01:00
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#define MICROPY_PY_MACHINE_SPI (1)
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2021-09-02 03:39:28 +01:00
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#define MICROPY_PY_MACHINE_SOFTSPI (1)
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2022-10-27 04:43:03 +01:00
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#define MICROPY_PY_MACHINE_TIMER (1)
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2023-02-12 13:15:08 +00:00
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#define MICROPY_SOFT_TIMER_TICKS_MS systick_ms
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2021-09-02 03:39:50 +01:00
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#define MICROPY_PY_ONEWIRE (1)
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2022-08-18 06:01:26 +01:00
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#define MICROPY_PY_PLATFORM (1)
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2020-01-20 11:25:51 +00:00
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2021-08-01 10:20:39 +01:00
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// fatfs configuration used in ffconf.h
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#define MICROPY_FATFS_ENABLE_LFN (1)
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#define MICROPY_FATFS_RPATH (2)
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#define MICROPY_FATFS_MAX_SS (4096)
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#define MICROPY_FATFS_LFN_CODE_PAGE 437 /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */
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2023-03-07 18:34:10 +00:00
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#ifndef MICROPY_PY_NETWORK
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2021-07-03 17:39:17 +01:00
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#define MICROPY_PY_NETWORK (1)
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2023-03-07 18:34:10 +00:00
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#endif
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2022-08-18 06:01:26 +01:00
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#ifndef MICROPY_PY_SOCKET
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#define MICROPY_PY_SOCKET (1)
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2023-03-07 18:34:10 +00:00
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#endif
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2022-08-18 06:01:26 +01:00
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#define MICROPY_PY_WEBSOCKET (MICROPY_PY_LWIP)
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2023-03-07 18:34:10 +00:00
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#define MICROPY_PY_WEBREPL (MICROPY_PY_LWIP)
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#define MICROPY_PY_LWIP_SOCK_RAW (MICROPY_PY_LWIP)
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2022-08-18 06:01:26 +01:00
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#define MICROPY_PY_SSL_FINALISER (MICROPY_PY_SSL)
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// #define MICROPY_PY_HASHLIB_MD5 (MICROPY_PY_SSL)
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#define MICROPY_PY_HASHLIB_SHA1 (MICROPY_PY_SSL)
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// #define MICROPY_PY_CRYPTOLIB (MICROPY_PY_SSL)
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2021-07-03 17:39:17 +01:00
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// Prevent the "LWIP task" from running.
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#define MICROPY_PY_LWIP_ENTER MICROPY_PY_PENDSV_ENTER
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#define MICROPY_PY_LWIP_REENTER MICROPY_PY_PENDSV_REENTER
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#define MICROPY_PY_LWIP_EXIT MICROPY_PY_PENDSV_EXIT
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2023-02-01 03:19:45 +00:00
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#ifndef MICROPY_PY_NETWORK_HOSTNAME_DEFAULT
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#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-mimxrt"
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#endif
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2021-07-03 17:39:17 +01:00
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// For regular code that wants to prevent "background tasks" from running.
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// These background tasks (LWIP, Bluetooth) run in PENDSV context.
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// TODO: Check for the settings of the STM32 port in irq.h
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2022-02-23 13:15:27 +00:00
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#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003)
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#define IRQ_PRI_PENDSV NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
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#define MICROPY_PY_PENDSV_ENTER uint32_t atomic_state = raise_irq_pri(IRQ_PRI_PENDSV);
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#define MICROPY_PY_PENDSV_REENTER atomic_state = raise_irq_pri(IRQ_PRI_PENDSV);
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#define MICROPY_PY_PENDSV_EXIT restore_irq_pri(atomic_state);
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2021-07-03 17:39:17 +01:00
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2020-01-20 11:25:51 +00:00
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// Hooks to add builtins
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2021-05-26 12:19:38 +01:00
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__attribute__((always_inline)) static inline void enable_irq(uint32_t state) {
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__set_PRIMASK(state);
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}
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__attribute__((always_inline)) static inline uint32_t disable_irq(void) {
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uint32_t state = __get_PRIMASK();
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2021-07-20 07:18:18 +01:00
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__disable_irq();
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2021-05-26 12:19:38 +01:00
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return state;
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}
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2021-11-10 12:59:09 +00:00
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static inline uint32_t raise_irq_pri(uint32_t pri) {
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uint32_t basepri = __get_BASEPRI();
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// If non-zero, the processor does not process any exception with a
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// priority value greater than or equal to BASEPRI.
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// When writing to BASEPRI_MAX the write goes to BASEPRI only if either:
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// - Rn is non-zero and the current BASEPRI value is 0
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// - Rn is non-zero and less than the current BASEPRI value
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pri <<= (8 - __NVIC_PRIO_BITS);
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__ASM volatile ("msr basepri_max, %0" : : "r" (pri) : "memory");
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return basepri;
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}
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// "basepri" should be the value returned from raise_irq_pri
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static inline void restore_irq_pri(uint32_t basepri) {
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__set_BASEPRI(basepri);
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}
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2021-05-26 12:19:38 +01:00
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#define MICROPY_BEGIN_ATOMIC_SECTION() disable_irq()
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#define MICROPY_END_ATOMIC_SECTION(state) enable_irq(state)
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2023-03-07 18:34:10 +00:00
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#if defined(IOMUX_TABLE_ENET)
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2021-07-03 17:39:17 +01:00
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extern const struct _mp_obj_type_t network_lan_type;
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#define MICROPY_HW_NIC_ETH { MP_ROM_QSTR(MP_QSTR_LAN), MP_ROM_PTR(&network_lan_type) },
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#else
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#define MICROPY_HW_NIC_ETH
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#endif
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2020-01-20 11:25:51 +00:00
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2022-03-09 22:54:44 +00:00
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#ifndef MICROPY_BOARD_NETWORK_INTERFACES
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#define MICROPY_BOARD_NETWORK_INTERFACES
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#endif
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2021-07-03 17:39:17 +01:00
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#define MICROPY_PORT_NETWORK_INTERFACES \
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MICROPY_HW_NIC_ETH \
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2022-03-09 22:54:44 +00:00
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MICROPY_BOARD_NETWORK_INTERFACES \
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2020-01-20 11:25:51 +00:00
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2021-10-20 20:24:20 +01:00
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#ifndef MICROPY_BOARD_ROOT_POINTERS
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#define MICROPY_BOARD_ROOT_POINTERS
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#endif
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2023-03-05 11:52:35 +00:00
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// Additional entries for use with pendsv_schedule_dispatch.
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#ifndef MICROPY_BOARD_PENDSV_ENTRIES
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#define MICROPY_BOARD_PENDSV_ENTRIES
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#endif
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2020-01-20 11:25:51 +00:00
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#define MP_STATE_PORT MP_STATE_VM
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// Miscellaneous settings
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2021-10-20 20:24:20 +01:00
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#ifndef MICROPY_EVENT_POLL_HOOK
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2020-01-20 11:25:51 +00:00
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#define MICROPY_EVENT_POLL_HOOK \
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do { \
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extern void mp_handle_pending(bool); \
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mp_handle_pending(true); \
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2022-10-22 20:28:42 +01:00
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__WFE(); \
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2020-01-20 11:25:51 +00:00
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} while (0);
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2021-10-20 20:24:20 +01:00
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#endif
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2020-01-20 11:25:51 +00:00
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#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((mp_uint_t)(p) | 1))
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2021-11-29 17:50:34 +00:00
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#define MP_HAL_CLEANINVALIDATE_DCACHE(addr, size) \
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(SCB_CleanInvalidateDCache_by_Addr((uint32_t *)((uint32_t)addr & ~0x1f), \
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((uint32_t)((uint8_t *)addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
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2021-05-26 12:19:38 +01:00
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#define MP_HAL_CLEAN_DCACHE(addr, size) \
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(SCB_CleanDCache_by_Addr((uint32_t *)((uint32_t)addr & ~0x1f), \
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((uint32_t)((uint8_t *)addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
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2020-01-20 11:25:51 +00:00
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#define MP_SSIZE_MAX (0x7fffffff)
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typedef int mp_int_t; // must be pointer size
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typedef unsigned mp_uint_t; // must be pointer size
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typedef long mp_off_t;
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2021-05-26 12:19:38 +01:00
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// Need an implementation of the log2 function which is not a macro.
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#define MP_NEED_LOG2 (1)
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2020-01-20 11:25:51 +00:00
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// Need to provide a declaration/definition of alloca()
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#include <alloca.h>
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