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micropython/ports/stm32/system_stm32.c

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Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
/*
all: Use the name MicroPython consistently in comments There were several different spellings of MicroPython present in comments, when there should be only one.
2017-06-30 08:22:17 +01:00
* This file is part of the MicroPython project, http://micropython.org/
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
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*
* Taken from ST Cube library and modified. See below for original header.
*
* The MIT License (MIT)
*
* Copyright (c) 2013, 2014 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
******************************************************************************
stmhal: Add STM32F7DISC and associated changes.
2015-07-28 19:13:33 +01:00
* @file system_stm32.c
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
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* @author MCD Application Team
* @version V1.0.1
* @date 26-February-2014
stmhal: Add STM32F7DISC and associated changes.
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* @brief CMSIS Cortex-M4/M7 Device Peripheral Access Layer System Source File.
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
stmhal: Add STM32F7DISC and associated changes.
2015-07-28 19:13:33 +01:00
* the "startup_stm32.s" file.
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
stmhal: Clean up some header includes.
2017-07-03 08:37:22 +01:00
#include "py/mphal.h"
stm32/powerctrl: Factor code to set RCC PLL and use it in startup. This ensures that on first boot the most optimal settings are used for the voltage scaling and flash latency (for F7 MCUs). This commit also provides more fine-grained control for the flash latency settings.
2018-09-24 07:27:35 +01:00
#include "powerctrl.h"
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
stm32: Add initial support for STM32WBxx MCUs. This new series of MCUs is similar to the L4 series with an additional Cortex-M0 coprocessor. The firmware for the wireless stack must be managed separately and MicroPython does not currently interface to it. Supported features so far include: RTC, UART, USB, internal flash filesystem.
2019-07-17 07:33:31 +01:00
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) || defined(STM32L4)
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
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void __fatal_error(const char *msg);
/**
* @brief System Clock Configuration
stmhal: L4: Adapt startup code, clock configuration and interrupts.
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*
* The system Clock is configured for F4/F7 as follows:
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* (HSx should be read as HSE or HSI depending on the value of MICROPY_HW_CLK_USE_HSI)
* System Clock source = PLL (HSx)
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
* SYSCLK(Hz) = 168000000
* HCLK(Hz) = 168000000
* AHB Prescaler = 1
* APB1 Prescaler = 4
* APB2 Prescaler = 2
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* HSx Frequency(Hz) = HSx_VALUE
* PLL_M = HSx_VALUE/1000000
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
* PLL_N = 336
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* PLL_P = 4
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
* PLL_Q = 7
* VDD(V) = 3.3
* Main regulator output voltage = Scale1 mode
* Flash Latency(WS) = 5
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
*
* The system Clock is configured for L4 as follows:
* System Clock source = PLL (MSI)
* SYSCLK(Hz) = 80000000
* HCLK(Hz) = 80000000
* AHB Prescaler = 1
* APB1 Prescaler = 1
* APB2 Prescaler = 1
* MSI Frequency(Hz) = MSI_VALUE (4000000)
* LSE Frequency(Hz) = 32768
* PLL_M = 1
* PLL_N = 40
* PLL_P = 7
* PLL_Q = 2
* PLL_R = 2 <= This is the source for SysClk, not as on F4/7 PLL_P
* Flash Latency(WS) = 4
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
* @param None
* @retval None
stmhal: Allow pyb.freq() function to change SYSCLK frequency. Eg pyb.freq(120000000) sets the CPU to 120MHz. The frequency can be set at any point in the code, and can be changed as many times as you like. Note that any active timers will need to be reconfigured after a freq change. Valid range is 24MHz to 168MHz (but not all freqs are supported). The code maintains a 48MHz clock for the USB at all times and it's possible to change the frequency at a USB REPL and keep the REPL alive (well, most of the time it stays, sometimes it resets the USB for some reason). Note that USB does not work with pyb.freq of 24MHz.
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*
* PLL is configured as follows:
*
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
* VCO_IN
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* F4/F7 = HSx / M
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
* L4 = MSI / M
* VCO_OUT
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* F4/F7 = HSx / M * N
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
* L4 = MSI / M * N
* PLLCLK
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* F4/F7 = HSx / M * N / P
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
* L4 = MSI / M * N / R
* PLL48CK
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* F4/F7 = HSx / M * N / Q
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
* L4 = MSI / M * N / Q USB Clock is obtained over PLLSAI1
stmhal: Allow pyb.freq() function to change SYSCLK frequency. Eg pyb.freq(120000000) sets the CPU to 120MHz. The frequency can be set at any point in the code, and can be changed as many times as you like. Note that any active timers will need to be reconfigured after a freq change. Valid range is 24MHz to 168MHz (but not all freqs are supported). The code maintains a 48MHz clock for the USB at all times and it's possible to change the frequency at a USB REPL and keep the REPL alive (well, most of the time it stays, sometimes it resets the USB for some reason). Note that USB does not work with pyb.freq of 24MHz.
2014-10-04 01:54:31 +01:00
*
* SYSCLK = PLLCLK
* HCLK = SYSCLK / AHB_PRESC
* PCLKx = HCLK / APBx_PRESC
*
* Constraints on parameters:
*
* VCO_IN between 1MHz and 2MHz (2MHz recommended)
* VCO_OUT between 192MHz and 432MHz
* HSE = 8MHz
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
* HSI = 16MHz
stmhal: Allow pyb.freq() function to change SYSCLK frequency. Eg pyb.freq(120000000) sets the CPU to 120MHz. The frequency can be set at any point in the code, and can be changed as many times as you like. Note that any active timers will need to be reconfigured after a freq change. Valid range is 24MHz to 168MHz (but not all freqs are supported). The code maintains a 48MHz clock for the USB at all times and it's possible to change the frequency at a USB REPL and keep the REPL alive (well, most of the time it stays, sometimes it resets the USB for some reason). Note that USB does not work with pyb.freq of 24MHz.
2014-10-04 01:54:31 +01:00
* M = 2 .. 63 (inclusive)
* N = 192 ... 432 (inclusive)
* P = 2, 4, 6, 8
* Q = 2 .. 15 (inclusive)
*
* AHB_PRESC=1,2,4,8,16,64,128,256,512
* APBx_PRESC=1,2,4,8,16
*
* Output clocks:
*
* CPU SYSCLK max 168MHz
* USB,RNG,SDIO PLL48CK must be 48MHz for USB
* AHB HCLK max 168MHz
* APB1 PCLK1 max 42MHz
* APB2 PCLK2 max 84MHz
*
* Timers run from APBx if APBx_PRESC=1, else 2x APBx
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
*/
void SystemClock_Config(void) {
stm32: For MCUs that have PLLSAI allow to set SYSCLK at 2MHz increments. MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO and RNG peripherals. In such cases the SYSCLK is not restricted to values that allow the system PLL to generate 48MHz, but can be any frequency. This patch allows such configurability for F7 MCUs, allowing the SYSCLK to be set in 2MHz increments via machine.freq(). PLLSAI will only be enabled if needed, and consumes about 1mA extra. This fine grained control of frequency is useful to get accurate SPI baudrates, for example.
2018-09-11 07:42:57 +01:00
#if defined(STM32F7)
// The DFU bootloader changes the clocksource register from its default power
// on reset value, so we set it back here, so the clocksources are the same
// whether we were started from DFU or from a power on reset.
RCC->DCKCFGR2 = 0;
#endif
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
#if defined(STM32H7)
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
#endif
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
/* Enable Power Control clock */
#if defined(STM32H7)
MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
#else
__PWR_CLK_ENABLE();
#endif
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#elif defined(STM32L4)
stmhal: Fix clock initialisation of L4 MCUs. There are 2 changes: - remove early initialisation of LSE and replaced it by LSEDRIVE config (there is no reason to call HAL_RCC_OscConfig twice). - add initialisation of the variables PLLSAI1Source and PLLSAI1M as they are needed in Cube HAL 1.8.1.
2017-09-02 18:46:23 +01:00
// Configure LSE Drive Capability
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
#endif
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
#if defined(STM32H7)
// Wait for PWR_FLAG_VOSRDY
while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {
}
#endif
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
/* Enable HSE Oscillator and activate PLL with HSE as source */
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
RCC_OscInitStruct.OscillatorType = MICROPY_HW_RCC_OSCILLATOR_TYPE;
RCC_OscInitStruct.HSEState = MICROPY_HW_RCC_HSE_STATE;
RCC_OscInitStruct.HSIState = MICROPY_HW_RCC_HSI_STATE;
stm32/system_stm32: Provide default value for HSI calibration. If HSI is used the calibration value must be valid. Fixes #4596.
2019-03-24 19:53:27 +00:00
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
#if defined(STM32H7)
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
#endif
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
RCC_OscInitStruct.PLL.PLLSource = MICROPY_HW_RCC_PLL_SRC;
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#elif defined(STM32L4)
stm32/system_stm32: Support selection of HSE and LSI on L4 MCUs. This commit adds the option to use HSE or MSI system clock, and LSE or LSI RTC clock, on L4 MCUs. Note that prior to this commit the default clocks on an L4 part were MSI and LSE. The defaults are now MSI and LSI. In mpconfigboard.h select the clock source via: #define MICROPY_HW_RTC_USE_LSE (0) or (1) #define MICROPY_HW_CLK_USE_HSE (0) or (1) and the PLLSAI1 N,P,Q,R settings: #define MICROPY_HW_CLK_PLLSAIN (12) #define MICROPY_HW_CLK_PLLSAIP (RCC_PLLP_DIV7) #define MICROPY_HW_CLK_PLLSAIQ (RCC_PLLQ_DIV2) #define MICROPY_HW_CLK_PLLSAIR (RCC_PLLR_DIV2)
2019-09-21 18:30:19 +01:00
#if MICROPY_HW_CLK_USE_HSE
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
#else
stm32: Add support for STM32L496 MCU.
2018-05-18 08:03:53 +01:00
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
stm32/system_stm32: Support selection of HSE and LSI on L4 MCUs. This commit adds the option to use HSE or MSI system clock, and LSE or LSI RTC clock, on L4 MCUs. Note that prior to this commit the default clocks on an L4 part were MSI and LSE. The defaults are now MSI and LSI. In mpconfigboard.h select the clock source via: #define MICROPY_HW_RTC_USE_LSE (0) or (1) #define MICROPY_HW_CLK_USE_HSE (0) or (1) and the PLLSAI1 N,P,Q,R settings: #define MICROPY_HW_CLK_PLLSAIN (12) #define MICROPY_HW_CLK_PLLSAIP (RCC_PLLP_DIV7) #define MICROPY_HW_CLK_PLLSAIQ (RCC_PLLQ_DIV2) #define MICROPY_HW_CLK_PLLSAIR (RCC_PLLR_DIV2)
2019-09-21 18:30:19 +01:00
#endif
#if MICROPY_HW_RTC_USE_LSE
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
#else
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
#endif
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
#endif
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
#if defined(STM32H7)
RCC_ClkInitStruct.ClockType |= (RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1);
#endif
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
#if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32F7)
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
#define FREQ_BKP BKP31R
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#elif defined(STM32L4)
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
#error Unsupported Processor
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
#else
#define FREQ_BKP BKP19R
#endif
uint32_t m = RTC->FREQ_BKP;
uint32_t n;
uint32_t p;
uint32_t q;
// 222111HH HHQQQQPP nNNNNNNN NNMMMMMM
uint32_t h = (m >> 22) & 0xf;
uint32_t b1 = (m >> 26) & 0x7;
uint32_t b2 = (m >> 29) & 0x7;
q = (m >> 18) & 0xf;
p = (((m >> 16) & 0x03) + 1) * 2;
n = (m >> 6) & 0x3ff;
m &= 0x3f;
if ((q < 2) || (q > 15) || (p > 8) || (p < 2) || (n < 192) || (n >= 433) || (m < 2)) {
m = MICROPY_HW_CLK_PLLM;
n = MICROPY_HW_CLK_PLLN;
p = MICROPY_HW_CLK_PLLP;
q = MICROPY_HW_CLK_PLLQ;
h = RCC_SYSCLK_DIV1;
b1 = RCC_HCLK_DIV4;
b2 = RCC_HCLK_DIV2;
} else {
h <<= 4;
b1 <<= 10;
b2 <<= 10;
}
RCC_OscInitStruct.PLL.PLLM = m; // MICROPY_HW_CLK_PLLM;
RCC_OscInitStruct.PLL.PLLN = n; // MICROPY_HW_CLK_PLLN;
RCC_OscInitStruct.PLL.PLLP = p; // MICROPY_HW_CLK_PLLP;
RCC_OscInitStruct.PLL.PLLQ = q; // MICROPY_HW_CLK_PLLQ;
all: Format code to add space after C++-style comment start. Note: the uncrustify configuration is explicitly set to 'add' instead of 'force' in order not to alter the comments which use extra spaces after // as a means of indenting text for clarity.
2020-04-16 08:13:57 +01:00
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
RCC_ClkInitStruct.AHBCLKDivider = h; // RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = b1; // RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = b2; // RCC_HCLK_DIV2;
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
#else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
RCC_OscInitStruct.PLL.PLLQ = MICROPY_HW_CLK_PLLQ;
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32L4) || defined(STM32H7)
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
#endif
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
#if defined(STM32H7)
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
#endif
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32F4) || defined(STM32F7)
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#elif defined(STM32L4)
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
#elif defined(STM32H7)
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
#endif
stmhal: Implement delayed RTC initialization with LSI fallback. If RTC is already running at boot then it's left alone. Otherwise, RTC is started at boot but startup function returns straight away. RTC startup is then finished the first time it is used. Fallback to LSI if LSE fails to start in a certain time. Also included: MICROPY_HW_CLK_LAST_FREQ hold pyb.freq() parameters in RTC backup reg MICROPY_HW_RTC_USE_US option to present datetime sub-seconds in microseconds MICROPY_HW_RTC_USE_CALOUT option to enable RTC calibration output CLK_LAST_FREQ and RTC_USE_CALOUT are enabled for PYBv1.0.
2015-11-07 11:03:12 +00:00
#endif
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
__fatal_error("HAL_RCC_OscConfig");
}
#if defined(STM32H7)
/* PLL3 for USB Clock */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
stm32/system_stm32: Introduce configuration defines for PLL3 settings. A board must be able to set the PLL3 values based on the HSE that it uses.
2018-10-24 21:52:36 +01:00
PeriphClkInitStruct.PLL3.PLL3M = MICROPY_HW_CLK_PLL3M;
PeriphClkInitStruct.PLL3.PLL3N = MICROPY_HW_CLK_PLL3N;
PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P;
PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q;
PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R;
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
}
#endif
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32F7)
stmhal: Add STM32F7DISC and associated changes.
2015-07-28 19:13:33 +01:00
/* Activate the OverDrive to reach the 200 MHz Frequency */
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
__fatal_error("HAL_PWREx_EnableOverDrive");
}
#endif
stm32: Add compile-time option to use HSI as clock source. To use HSI instead of HSE define MICROPY_HW_CLK_USE_HSI as 1 in the board configuration file. The default is to use HSE. HSI has been made the default for the NUCLEO_F401RE board to serve as an example, and because early revisions of this board need a hardware modification to get HSE working.
2019-03-03 23:50:23 +00:00
uint32_t vco_out = RCC_OscInitStruct.PLL.PLLN * (MICROPY_HW_CLK_VALUE / 1000000) / RCC_OscInitStruct.PLL.PLLM;
stm32/powerctrl: Factor code that configures PLLSAI on F7 MCUs.
2018-09-24 07:47:06 +01:00
uint32_t sysclk_mhz = vco_out / RCC_OscInitStruct.PLL.PLLP;
bool need_pllsai = vco_out % 48 != 0;
if (powerctrl_rcc_clock_config_pll(&RCC_ClkInitStruct, sysclk_mhz, need_pllsai) != 0) {
stm32/powerctrl: Factor code to set RCC PLL and use it in startup. This ensures that on first boot the most optimal settings are used for the voltage scaling and flash latency (for F7 MCUs). This commit also provides more fine-grained control for the flash latency settings.
2018-09-24 07:27:35 +01:00
__fatal_error("HAL_RCC_ClockConfig");
}
stmhal: M7 Reset clocksources changed by DFU bootloader The DFU bootloader on the ST32F7 chip changes the clocksource for various possible boot sources (UART1, UART3, I2C1-3). This commit resets those clock sources back to their cold reset values.
2015-08-02 04:22:08 +01:00
stm32/system_stm32: Add H7 MCU system initialisation.
2018-02-22 18:31:38 +00:00
#if defined(STM32H7)
/* Activate CSI clock mandatory for I/O Compensation Cell*/
__HAL_RCC_CSI_ENABLE();
/* Enable SYSCFG clock mandatory for I/O Compensation Cell */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable the I/O Compensation Cell */
HAL_EnableCompensationCell();
/* Enable the USB voltage level detector */
HAL_PWREx_EnableUSBVoltageDetector();
#endif
stm32: Use STM32xx macros instead of MCU_SERIES_xx to select MCU type. The CMSIS files for the STM32 range provide macros to distinguish between the different MCU series: STM32F4, STM32F7, STM32H7, STM32L4, etc. Prefer to use these instead of custom ones.
2018-03-16 23:42:50 +00:00
#if defined(STM32L4)
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
// Enable MSI-Hardware auto calibration mode with LSE
HAL_RCCEx_EnableMSIPLLMode();
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2C1
| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC
| RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
stm32/system_stm32: Support selection of HSE and LSI on L4 MCUs. This commit adds the option to use HSE or MSI system clock, and LSE or LSI RTC clock, on L4 MCUs. Note that prior to this commit the default clocks on an L4 part were MSI and LSE. The defaults are now MSI and LSI. In mpconfigboard.h select the clock source via: #define MICROPY_HW_RTC_USE_LSE (0) or (1) #define MICROPY_HW_CLK_USE_HSE (0) or (1) and the PLLSAI1 N,P,Q,R settings: #define MICROPY_HW_CLK_PLLSAIN (12) #define MICROPY_HW_CLK_PLLSAIP (RCC_PLLP_DIV7) #define MICROPY_HW_CLK_PLLSAIQ (RCC_PLLQ_DIV2) #define MICROPY_HW_CLK_PLLSAIR (RCC_PLLR_DIV2)
2019-09-21 18:30:19 +01:00
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1;
stm32/system_stm32: Support selection of HSE and LSI on L4 MCUs. This commit adds the option to use HSE or MSI system clock, and LSE or LSI RTC clock, on L4 MCUs. Note that prior to this commit the default clocks on an L4 part were MSI and LSE. The defaults are now MSI and LSI. In mpconfigboard.h select the clock source via: #define MICROPY_HW_RTC_USE_LSE (0) or (1) #define MICROPY_HW_CLK_USE_HSE (0) or (1) and the PLLSAI1 N,P,Q,R settings: #define MICROPY_HW_CLK_PLLSAIN (12) #define MICROPY_HW_CLK_PLLSAIP (RCC_PLLP_DIV7) #define MICROPY_HW_CLK_PLLSAIQ (RCC_PLLQ_DIV2) #define MICROPY_HW_CLK_PLLSAIR (RCC_PLLR_DIV2)
2019-09-21 18:30:19 +01:00
#if MICROPY_HW_RTC_USE_LSE
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#else
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#endif
#if MICROPY_HW_CLK_USE_HSE
PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 1; // MICROPY_HW_CLK_PLLSAIM;
PeriphClkInitStruct.PLLSAI1.PLLSAI1N = MICROPY_HW_CLK_PLLSAIN;
PeriphClkInitStruct.PLLSAI1.PLLSAI1P = MICROPY_HW_CLK_PLLSAIP;
PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = MICROPY_HW_CLK_PLLSAIQ;
PeriphClkInitStruct.PLLSAI1.PLLSAI1R = MICROPY_HW_CLK_PLLSAIR;
#else
/* PLLSAI is used to clock USB, ADC, I2C1 and RNG. The frequency is
MSI(4MHz)/PLLM(1)*PLLSAI1N(24)/PLLSAIQ(2) = 48MHz. See the STM32CubeMx
application or the reference manual. */
stmhal: Fix clock initialisation of L4 MCUs. There are 2 changes: - remove early initialisation of LSE and replaced it by LSEDRIVE config (there is no reason to call HAL_RCC_OscConfig twice). - add initialisation of the variables PLLSAI1Source and PLLSAI1M as they are needed in Cube HAL 1.8.1.
2017-09-02 18:46:23 +01:00
PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 1;
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24;
PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
PeriphClkInitStruct.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
stm32/system_stm32: Support selection of HSE and LSI on L4 MCUs. This commit adds the option to use HSE or MSI system clock, and LSE or LSI RTC clock, on L4 MCUs. Note that prior to this commit the default clocks on an L4 part were MSI and LSE. The defaults are now MSI and LSI. In mpconfigboard.h select the clock source via: #define MICROPY_HW_RTC_USE_LSE (0) or (1) #define MICROPY_HW_CLK_USE_HSE (0) or (1) and the PLLSAI1 N,P,Q,R settings: #define MICROPY_HW_CLK_PLLSAIN (12) #define MICROPY_HW_CLK_PLLSAIP (RCC_PLLP_DIV7) #define MICROPY_HW_CLK_PLLSAIQ (RCC_PLLQ_DIV2) #define MICROPY_HW_CLK_PLLSAIR (RCC_PLLR_DIV2)
2019-09-21 18:30:19 +01:00
#endif
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK
| RCC_PLLSAI1_48M2CLK
| RCC_PLLSAI1_ADC1CLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
}
__PWR_CLK_ENABLE();
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
stm32/irq: Define IRQ priorities directly as encoded hardware values. For a given IRQn (eg UART) there's no need to carry around both a PRI and SUBPRI value (eg IRQ_PRI_UART, IRQ_SUBPRI_UART). Instead, the IRQ_PRI_UART value has been changed in this patch to be the encoded hardware value, using NVIC_EncodePriority. This way the NVIC_SetPriority function can be used directly, instead of going through HAL_NVIC_SetPriority which must do extra processing to encode the PRI+SUBPRI. For a priority grouping of 4 (4 bits for preempt priority, 0 bits for the sub-priority), which is used in the stm32 port, the IRQ_PRI_xxx constants remain unchanged in their value. This patch also "fixes" the use of raise_irq_pri() which should be passed the encoded value (but as mentioned above the unencoded value is the same as the encoded value for priority grouping 4, so there was no bug from this error).
2018-05-02 05:41:02 +01:00
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, TICK_INT_PRIORITY, 0));
stmhal: L4: Adapt startup code, clock configuration and interrupts.
2016-03-23 21:39:31 +00:00
#endif
stm32/system_stm32: Enable DBGMCU in low-power modes for debug builds.
2020-12-07 22:22:17 +00:00
#if defined(STM32H7) && !defined(NDEBUG)
// Enable the Debug Module in low-power modes.
DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEPD1 | DBGMCU_CR_DBG_STOPD1 | DBGMCU_CR_DBG_STANDBYD1);
#endif
Add license header to (almost) all files. Blanket wide to all .c and .h files. Some files originating from ST are difficult to deal with (license wise) so it was left out of those. Also merged modpyb.h, modos.h, modstm.h and modtime.h in stmhal/.
2014-05-03 23:27:38 +01:00
}
stm32: Add initial support for STM32WBxx MCUs. This new series of MCUs is similar to the L4 series with an additional Cortex-M0 coprocessor. The firmware for the wireless stack must be managed separately and MicroPython does not currently interface to it. Supported features so far include: RTC, UART, USB, internal flash filesystem.
2019-07-17 07:33:31 +01:00
#endif