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micropython/ports/stm32/boards/stm32f405_af.csv

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Add a comma to make the .csv look proper in github
2014-05-31 06:18:52 +01:00
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,,,ADC
Fixed TIM2_CH1 definition. TIM2_CH1_ETR is really bundling 2 functions to the same pin: TIM2_CH1 (where its used as a channel) TIM2_ETR (where iss used as an external trigger). I fixed most of these a while back, but it looks like I missed this one.
2014-10-22 18:06:06 +01:00
PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0
stm32/boards/stm32f405_af.csv: Fix typo in ETH_RMII_REF_CLK on PA1.
2019-11-08 02:21:10 +00:00
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,,EVENTOUT,ADC123_IN1
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,ETH_MDIO,,,,EVENTOUT,ADC123_IN2
Add missing commas to stm32f4xx-af.csv
2014-06-03 07:04:41 +01:00
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT,ADC123_IN3
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT,ADC12_IN4
stmhal: Fix pin af definition: TIM2_CH1_ETR -> TIM2_CH1/TIM2_ETR.
2014-10-23 22:07:24 +01:00
PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT,ADC12_IN5
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCK,,EVENTOUT,ADC12_IN6
PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,,,,EVENTOUT,ADC12_IN7
Add missing commas to stm32f4xx-af.csv
2014-06-03 07:04:41 +01:00
PortA,PA8,MCO1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT,
PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT,
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT,
PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT,
stm32/boards/*_af.csv: Make consistent use of JTMS, JTCK, SWDIO, SWCLK. 5-pin JTAG and 2-pin SWD are logically separate interfaces so encode them in the AF tables as separate entries (separated by /, not -).
2017-12-01 03:51:36 +00:00
PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT,
Add missing commas to stm32f4xx-af.csv
2014-06-03 07:04:41 +01:00
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT,
Fix PB0 ADC typo. This also adds a bunch of slashes separating pin that have multiple functions.
2014-05-02 22:01:23 +01:00
PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT,ADC12_IN8
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT,ADC12_IN9
Add missing commas to stm32f4xx-af.csv
2014-06-03 07:04:41 +01:00
PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT,
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT,
PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,,,,,,,EVENTOUT,
PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,,DCMI_D10,,EVENTOUT,
PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,CAN2_TX,,,,DCMI_D5,,EVENTOUT,
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FSMC_NL,DCMI_VSYNC,,EVENTOUT,
PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDIO_D4,DCMI_D6,,EVENTOUT,
PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDIO_D5,DCMI_D7,,EVENTOUT,
PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT,
PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT,
PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT,
PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT,
PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,I2S2ext_SD,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT,
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
PortC,PC0,,,,,,,,,,,OTG_HS_ULPI_STP,,,,,EVENTOUT,ADC123_IN10
PortC,PC1,,,,,,,,,,,,ETH_MDC,,,,EVENTOUT,ADC123_IN11
PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,,,,EVENTOUT,ADC123_IN12
PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,,,,EVENTOUT,ADC123_IN13
PortC,PC4,,,,,,,,,,,,ETH_MII_RXD0/ETH_RMII_RXD0,,,,EVENTOUT,ADC123_IN14
PortC,PC5,,,,,,,,,,,,ETH_MII_RXD1/ETH_RMII_RXD1,,,,EVENTOUT,ADC123_IN15
Add missing commas to stm32f4xx-af.csv
2014-06-03 07:04:41 +01:00
PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,DCMI_D0,,EVENTOUT,
PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,DCMI_D1,,EVENTOUT,
PortC,PC8,,,TIM3_CH3,TIM8_CH3,,,,,USART6_CK,,,,SDIO_D0,DCMI_D2,,EVENTOUT,
PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,,,,,,SDIO_D1,DCMI_D3,,EVENTOUT,
PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,,SDIO_D2,DCMI_D8,,EVENTOUT,
PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,USART3_RX,UART4_RX,,,,SDIO_D3,DCMI_D4,,EVENTOUT,
PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDIO_CK,DCMI_D9,,EVENTOUT,
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD0,,,,,,,,,,CAN1_RX,,,FSMC_D2,,,EVENTOUT,
PortD,PD1,,,,,,,,,,CAN1_TX,,,FSMC_D3,,,EVENTOUT,
PortD,PD2,,,TIM3_ETR,,,,,,UART5_RX,,,,SDIO_CMD,DCMI_D11,,EVENTOUT,
PortD,PD3,,,,,,,,USART2_CTS,,,,,FSMC_CLK,,,EVENTOUT,
PortD,PD4,,,,,,,,USART2_RTS,,,,,FSMC_NOE,,,EVENTOUT,
PortD,PD5,,,,,,,,USART2_TX,,,,,FSMC_NWE,,,EVENTOUT,
PortD,PD6,,,,,,,,USART2_RX,,,,,FSMC_NWAIT,,,EVENTOUT,
PortD,PD7,,,,,,,,USART2_CK,,,,,FSMC_NE1/FSMC_NCE2,,,EVENTOUT,
PortD,PD8,,,,,,,,USART3_TX,,,,,FSMC_D13,,,EVENTOUT,
PortD,PD9,,,,,,,,USART3_RX,,,,,FSMC_D14,,,EVENTOUT,
PortD,PD10,,,,,,,,USART3_CK,,,,,FSMC_D15,,,EVENTOUT,
PortD,PD11,,,,,,,,USART3_CTS,,,,,FSMC_A16,,,EVENTOUT,
PortD,PD12,,,TIM4_CH1,,,,,USART3_RTS,,,,,FSMC_A17,,,EVENTOUT,
PortD,PD13,,,TIM4_CH2,,,,,,,,,,FSMC_A18,,,EVENTOUT,
PortD,PD14,,,TIM4_CH3,,,,,,,,,,FSMC_D0,,,EVENTOUT,
PortD,PD15,,,TIM4_CH4,,,,,,,,,,FSMC_D1,,,EVENTOUT,
PortE,PE0,,,TIM4_ETR,,,,,,,,,,FSMC_NBL0,DCMI_D2,,EVENTOUT,
PortE,PE1,,,,,,,,,,,,,FSMC_NBL1,DCMI_D3,,EVENTOUT,
PortE,PE2,TRACECLK,,,,,,,,,,,ETH_MII_TXD3,FSMC_A23,,,EVENTOUT,
PortE,PE3,TRACED0,,,,,,,,,,,,FSMC_A19,,,EVENTOUT,
PortE,PE4,TRACED1,,,,,,,,,,,,FSMC_A20,DCMI_D4,,EVENTOUT,
PortE,PE5,TRACED2,,,TIM9_CH1,,,,,,,,,FSMC_A21,DCMI_D6,,EVENTOUT,
PortE,PE6,TRACED3,,,TIM9_CH2,,,,,,,,,FSMC_A22,DCMI_D7,,EVENTOUT,
PortE,PE7,,TIM1_ETR,,,,,,,,,,,FSMC_D4,,,EVENTOUT,
PortE,PE8,,TIM1_CH1N,,,,,,,,,,,FSMC_D5,,,EVENTOUT,
PortE,PE9,,TIM1_CH1,,,,,,,,,,,FSMC_D6,,,EVENTOUT,
PortE,PE10,,TIM1_CH2N,,,,,,,,,,,FSMC_D7,,,EVENTOUT,
PortE,PE11,,TIM1_CH2,,,,,,,,,,,FSMC_D8,,,EVENTOUT,
PortE,PE12,,TIM1_CH3N,,,,,,,,,,,FSMC_D9,,,EVENTOUT,
PortE,PE13,,TIM1_CH3,,,,,,,,,,,FSMC_D10,,,EVENTOUT,
PortE,PE14,,TIM1_CH4,,,,,,,,,,,FSMC_D11,,,EVENTOUT,
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FSMC_D12,,,EVENTOUT,
PortF,PF0,,,,,I2C2_SDA,,,,,,,,FSMC_A0,,,EVENTOUT,
PortF,PF1,,,,,I2C2_SCL,,,,,,,,FSMC_A1,,,EVENTOUT,
PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FSMC_A2,,,EVENTOUT,
stmhal - fixed up adc stuff Added support for the ADC channels and mappings to make_pins.py I'm not sure if the hal properly deals with the channel 16/18 differences between the 40x and 42x. It seems to deal with it partially. This particular aspect will need testing on a 42x or 43x.
2014-03-24 17:49:23 +00:00
PortF,PF3,,,,,,,,,,,,,FSMC_A3,,,EVENTOUT,ADC3_IN9
PortF,PF4,,,,,,,,,,,,,FSMC_A4,,,EVENTOUT,ADC3_IN14
PortF,PF5,,,,,,,,,,,,,FSMC_A5,,,EVENTOUT,ADC3_IN15
PortF,PF6,,,,TIM10_CH1,,,,,,,,,FSMC_NIORD,,,EVENTOUT,ADC3_IN4
PortF,PF7,,,,TIM11_CH1,,,,,,,,,FSMC_NREG,,,EVENTOUT,ADC3_IN5
PortF,PF8,,,,,,,,,,TIM13_CH1,,,FSMC_NIOWR,,,EVENTOUT,ADC3_IN6
PortF,PF9,,,,,,,,,,TIM14_CH1,,,FSMC_CD,,,EVENTOUT,ADC3_IN7
PortF,PF10,,,,,,,,,,,,,FSMC_INTR,,,EVENTOUT,ADC3_IN8
Add missing commas to stm32f4xx-af.csv
2014-06-03 07:04:41 +01:00
PortF,PF11,,,,,,,,,,,,,,DCMI_D12,,EVENTOUT,
PortF,PF12,,,,,,,,,,,,,FSMC_A6,,,EVENTOUT,
PortF,PF13,,,,,,,,,,,,,FSMC_A7,,,EVENTOUT,
PortF,PF14,,,,,,,,,,,,,FSMC_A8,,,EVENTOUT,
PortF,PF15,,,,,,,,,,,,,FSMC_A9,,,EVENTOUT,
PortG,PG0,,,,,,,,,,,,,FSMC_A10,,,EVENTOUT,
PortG,PG1,,,,,,,,,,,,,FSMC_A11,,,EVENTOUT,
PortG,PG2,,,,,,,,,,,,,FSMC_A12,,,EVENTOUT,
PortG,PG3,,,,,,,,,,,,,FSMC_A13,,,EVENTOUT,
PortG,PG4,,,,,,,,,,,,,FSMC_A14,,,EVENTOUT,
PortG,PG5,,,,,,,,,,,,,FSMC_A15,,,EVENTOUT,
PortG,PG6,,,,,,,,,,,,,FSMC_INT2,,,EVENTOUT,
PortG,PG7,,,,,,,,,USART6_CK,,,,FSMC_INT3,,,EVENTOUT,
PortG,PG8,,,,,,,,,USART6_RTS,,,ETH_PPS_OUT,,,,EVENTOUT,
PortG,PG9,,,,,,,,,USART6_RX,,,,FSMC_NE2/FSMC_NCE3,,,EVENTOUT,
PortG,PG10,,,,,,,,,,,,,FSMC_NCE4_1/FSMC_NE3,,,EVENTOUT,
PortG,PG11,,,,,,,,,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,FSMC_NCE4_2,,,EVENTOUT,
PortG,PG12,,,,,,,,,USART6_RTS,,,,FSMC_NE4,,,EVENTOUT,
PortG,PG13,,,,,,,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FSMC_A24,,,EVENTOUT,
PortG,PG14,,,,,,,,,USART6_TX,,,ETH_MII_TXD1/ETH_RMII_TXD1,FSMC_A25,,,EVENTOUT,
PortG,PG15,,,,,,,,,USART6_CTS,,,,,DCMI_D13,,EVENTOUT,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH2,,,,,,,,,,,,ETH_MII_CRS,,,,EVENTOUT,
PortH,PH3,,,,,,,,,,,,ETH_MII_COL,,,,EVENTOUT,
PortH,PH4,,,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT,
PortH,PH5,,,,,I2C2_SDA,,,,,,,,,,,EVENTOUT,
PortH,PH6,,,,,I2C2_SMBA,,,,,TIM12_CH1,,ETH_MII_RXD2,,,,EVENTOUT,
PortH,PH7,,,,,I2C3_SCL,,,,,,,ETH_MII_RXD3,,,,EVENTOUT,
PortH,PH8,,,,,I2C3_SDA,,,,,,,,,DCMI_HSYNC,,EVENTOUT,
PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,,DCMI_D0,,EVENTOUT,
PortH,PH10,,,TIM5_CH1,,,,,,,,,,,DCMI_D1,,EVENTOUT,
PortH,PH11,,,TIM5_CH2,,,,,,,,,,,DCMI_D2,,EVENTOUT,
PortH,PH12,,,TIM5_CH3,,,,,,,,,,,DCMI_D3,,EVENTOUT,
PortH,PH13,,,,TIM8_CH1N,,,,,,CAN1_TX,,,,,,EVENTOUT,
PortH,PH14,,,,TIM8_CH2N,,,,,,,,,,DCMI_D4,,EVENTOUT,
PortH,PH15,,,,TIM8_CH3N,,,,,,,,,,DCMI_D11,,EVENTOUT,
PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,,DCMI_D13,,EVENTOUT,
PortI,PI1,,,,,,SPI2_SCK/I2S2_CK,,,,,,,,DCMI_D8,,EVENTOUT,
PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,I2S2ext_SD,,,,,,,DCMI_D9,,EVENTOUT,
PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,,DCMI_D10,,EVENTOUT,
PortI,PI4,,,,TIM8_BKIN,,,,,,,,,,DCMI_D5,,EVENTOUT,
PortI,PI5,,,,TIM8_CH1,,,,,,,,,,DCMI_VSYNC,,EVENTOUT,
PortI,PI6,,,,TIM8_CH2,,,,,,,,,,DCMI_D6,,EVENTOUT,
PortI,PI7,,,,TIM8_CH3,,,,,,,,,,DCMI_D7,,EVENTOUT,
PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT,
PortI,PI9,,,,,,,,,,CAN1_RX,,,,,,EVENTOUT,
PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,,,,EVENTOUT,
PortI,PI11,,,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT,