393 lines
20 KiB
C
393 lines
20 KiB
C
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//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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#ifndef __HW_DTHE_H__
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#define __HW_DTHE_H__
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//*****************************************************************************
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//
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// The following are defines for the DTHE register offsets.
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//
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//*****************************************************************************
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#define DTHE_O_SHA_IM 0x00000810
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#define DTHE_O_SHA_RIS 0x00000814
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#define DTHE_O_SHA_MIS 0x00000818
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#define DTHE_O_SHA_IC 0x0000081C
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#define DTHE_O_AES_IM 0x00000820
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#define DTHE_O_AES_RIS 0x00000824
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#define DTHE_O_AES_MIS 0x00000828
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#define DTHE_O_AES_IC 0x0000082C
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#define DTHE_O_DES_IM 0x00000830
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#define DTHE_O_DES_RIS 0x00000834
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#define DTHE_O_DES_MIS 0x00000838
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#define DTHE_O_DES_IC 0x0000083C
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#define DTHE_O_EIP_CGCFG 0x00000A00
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#define DTHE_O_EIP_CGREQ 0x00000A04
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#define DTHE_O_CRC_CTRL 0x00000C00
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#define DTHE_O_CRC_SEED 0x00000C10
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#define DTHE_O_CRC_DIN 0x00000C14
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#define DTHE_O_CRC_RSLT_PP 0x00000C18
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#define DTHE_O_RAND_KEY0 0x00000F00
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#define DTHE_O_RAND_KEY1 0x00000F04
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#define DTHE_O_RAND_KEY2 0x00000F08
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#define DTHE_O_RAND_KEY3 0x00000F0C
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_SHAMD5_IMST register.
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//
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//******************************************************************************
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#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is
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// raised when DMA writes last word
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// of input data to internal FIFO of
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// the engine
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#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is
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// raised when DMA complets the
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// output context movement from
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// internal register
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#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is
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// raised when DMA complets Context
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// write to internal register
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_SHAMD5_IRIS register.
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//
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//******************************************************************************
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#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done
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#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done
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#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_SHAMD5_IMIS register.
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//
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//******************************************************************************
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#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done
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#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done
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#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_SHAMD5_ICIS register.
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//
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//******************************************************************************
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#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done”
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// flag
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#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done” flag
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#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done” flag
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_AES_IMST register.
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//
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//******************************************************************************
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#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is
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// raised when DMA finishes writing
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// last word of the process result
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#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is
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// raised when DMA writes last word
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// of input data to internal FIFO of
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// the engine
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#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is
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// raised when DMA complets the
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// output context movement from
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// internal register
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#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is
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// raised when DMA complets Context
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// write to internal register
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_AES_IRIS register.
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//
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//******************************************************************************
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#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done
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#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done
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#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done
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#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_AES_IMIS register.
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//
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//******************************************************************************
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#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done
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#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done
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#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done
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#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_AES_ICIS register.
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//
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//******************************************************************************
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#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement
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// done” flag
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#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done”
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// flag
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#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done” flag
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#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done” flag
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_DES_IMST register.
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//
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//******************************************************************************
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#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is
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// raised when DMA finishes writing
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// last word of the process result
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#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is
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// raised when DMA writes last word
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// of input data to internal FIFO of
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// the engine
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#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is
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// raised when DMA complets Context
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// write to internal register
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_DES_IRIS register.
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//
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//******************************************************************************
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#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done
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#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done
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#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_DES_IMIS register.
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//
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//******************************************************************************
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#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done
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#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done
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#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_DES_ICIS register.
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//
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//******************************************************************************
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#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement
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// done” flag
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#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done”
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// flag
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#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done” flag
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_EIP_CGCFG register.
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//
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//******************************************************************************
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#define DTHE_EIP_CGCFG_EIP29_CFG \
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0x00000010 // Clock gating protocol setting
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// for EIP29T. 0 – Follow direct
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// protocol 1 – Follow idle_req/ack
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// protocol.
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#define DTHE_EIP_CGCFG_EIP75_CFG \
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0x00000008 // Clock gating protocol setting
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// for EIP75T. 0 – Follow direct
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// protocol 1 – Follow idle_req/ack
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// protocol.
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#define DTHE_EIP_CGCFG_EIP16_CFG \
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0x00000004 // Clock gating protocol setting
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// for DES. 0 – Follow direct
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// protocol 1 – Follow idle_req/ack
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// protocol.
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#define DTHE_EIP_CGCFG_EIP36_CFG \
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0x00000002 // Clock gating protocol setting
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// for AES. 0 – Follow direct
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// protocol 1 – Follow idle_req/ack
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// protocol.
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#define DTHE_EIP_CGCFG_EIP57_CFG \
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0x00000001 // Clock gating protocol setting
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// for SHAMD5. 0 – Follow direct
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// protocol 1 – Follow idle_req/ack
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// protocol.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// DTHE_O_EIP_CGREQ register.
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//
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//******************************************************************************
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#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5” write “1” to lower
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// bits [4:0] will set the bit.
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// Write “0” will be ignored When
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// “0x2” write “1” to lower bit
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// [4:0] will clear the bit. Write
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// “0” will be ignored for other key
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// value, regular read write
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// operation
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#define DTHE_EIP_CGREQ_Key_S 28
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#define DTHE_EIP_CGREQ_EIP29_REQ \
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0x00000010 // 0 – request clock gating 1 –
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// request to un-gate the clock.
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#define DTHE_EIP_CGREQ_EIP75_REQ \
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0x00000008 // 0 – request clock gating 1 –
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// request to un-gate the clock.
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#define DTHE_EIP_CGREQ_EIP16_REQ \
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0x00000004 // 0 – request clock gating 1 –
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// request to un-gate the clock.
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#define DTHE_EIP_CGREQ_EIP36_REQ \
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0x00000002 // 0 – request clock gating 1 –
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// request to un-gate the clock.
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#define DTHE_EIP_CGREQ_EIP57_REQ \
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0x00000001 // 0 – request clock gating 1 –
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// request to un-gate the clock.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register.
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//
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//******************************************************************************
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#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED
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// register context as starting
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// value 10 – all “zero” 11 – all
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// “one” This is self clearing. With
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// first write to data register this
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// value clears to zero and remain
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// zero for rest of the operation
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// unless written again
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#define DTHE_CRC_CTRL_INIT_S 13
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#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8
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// bit
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#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result
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// before storing to CRC_RSLT_PP0
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#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result
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// byte before storing to
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// CRC_RSLT_PP0. applicable for all
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// bytes in word
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#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For
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// all bytes in word
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#define DTHE_CRC_CTRL_ENDIAN_M \
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0x00000030 // Endian control [0] – swap byte
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// in half-word [1] – swap half word
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#define DTHE_CRC_CTRL_ENDIAN_S 4
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#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 –
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// polynomial 0x8005 0001 –
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// polynomial 0x1021 0010 –
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// polynomial 0x4C11DB7 0011 –
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// polynomial 0x1EDC6F41 1000 – TCP
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// checksum TYPE in DTHE_S_CRC_CTRL
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// & DTHE_S_CRC_CTRL should be
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// exclusive
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#define DTHE_CRC_CTRL_TYPE_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the DTHE_O_CRC_SEED register.
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//
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//******************************************************************************
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#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and
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// checksum operation. Please see
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// CTRL register for more detail.
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// This resister also holds the
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// latest result of CRC or checksum
|
|||
|
|
// operation
|
|||
|
|
#define DTHE_CRC_SEED_SEED_S 0
|
|||
|
|
//******************************************************************************
|
|||
|
|
//
|
|||
|
|
// The following are defines for the bit fields in the DTHE_O_CRC_DIN register.
|
|||
|
|
//
|
|||
|
|
//******************************************************************************
|
|||
|
|
#define DTHE_CRC_DIN_DATA_IN_M \
|
|||
|
|
0xFFFFFFFF // Input data for CRC or checksum
|
|||
|
|
// operation
|
|||
|
|
|
|||
|
|
#define DTHE_CRC_DIN_DATA_IN_S 0
|
|||
|
|
//******************************************************************************
|
|||
|
|
//
|
|||
|
|
// The following are defines for the bit fields in the
|
|||
|
|
// DTHE_O_CRC_RSLT_PP register.
|
|||
|
|
//
|
|||
|
|
//******************************************************************************
|
|||
|
|
#define DTHE_CRC_RSLT_PP_RSLT_PP_M \
|
|||
|
|
0xFFFFFFFF // Input data for CRC or checksum
|
|||
|
|
// operation
|
|||
|
|
|
|||
|
|
#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0
|
|||
|
|
//******************************************************************************
|
|||
|
|
//
|
|||
|
|
// The following are defines for the bit fields in the
|
|||
|
|
// DTHE_O_RAND_KEY0 register.
|
|||
|
|
//
|
|||
|
|
//******************************************************************************
|
|||
|
|
#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key
|
|||
|
|
// [31:0]
|
|||
|
|
#define DTHE_RAND_KEY0_KEY_S 0
|
|||
|
|
//******************************************************************************
|
|||
|
|
//
|
|||
|
|
// The following are defines for the bit fields in the
|
|||
|
|
// DTHE_O_RAND_KEY1 register.
|
|||
|
|
//
|
|||
|
|
//******************************************************************************
|
|||
|
|
#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key
|
|||
|
|
// [63:32]
|
|||
|
|
#define DTHE_RAND_KEY1_KEY_S 0
|
|||
|
|
//******************************************************************************
|
|||
|
|
//
|
|||
|
|
// The following are defines for the bit fields in the
|
|||
|
|
// DTHE_O_RAND_KEY2 register.
|
|||
|
|
//
|
|||
|
|
//******************************************************************************
|
|||
|
|
#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key
|
|||
|
|
// [95:34]
|
|||
|
|
#define DTHE_RAND_KEY2_KEY_S 0
|
|||
|
|
//******************************************************************************
|
|||
|
|
//
|
|||
|
|
// The following are defines for the bit fields in the
|
|||
|
|
// DTHE_O_RAND_KEY3 register.
|
|||
|
|
//
|
|||
|
|
//******************************************************************************
|
|||
|
|
#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key
|
|||
|
|
// [127:96]
|
|||
|
|
#define DTHE_RAND_KEY3_KEY_S 0
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
#endif // __HW_DTHE_H__
|