2014-05-03 23:27:38 +01:00
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/*
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2017-06-30 08:22:17 +01:00
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* This file is part of the MicroPython project, http://micropython.org/
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2014-05-03 23:27:38 +01:00
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2014-03-15 12:54:48 +00:00
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#include <stdio.h>
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2015-01-01 21:06:20 +00:00
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#include "py/runtime.h"
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2018-07-31 08:24:10 +01:00
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#include "extint.h"
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2014-03-15 12:54:48 +00:00
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#include "rtc.h"
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2015-10-31 17:44:20 +00:00
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#include "irq.h"
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2014-03-15 12:54:48 +00:00
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2019-07-17 07:33:31 +01:00
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#if defined(STM32WB)
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#define RCC_CSR_LSION RCC_CSR_LSI1ON
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#define RCC_FLAG_LSIRDY RCC_FLAG_LSI1RDY
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#define RCC_OSCILLATORTYPE_LSI RCC_OSCILLATORTYPE_LSI1
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#define __HAL_RCC_LSI_ENABLE __HAL_RCC_LSI1_ENABLE
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#define __HAL_RCC_LSI_DISABLE __HAL_RCC_LSI1_DISABLE
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#endif
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2014-05-03 12:40:53 +01:00
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/// \moduleref pyb
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/// \class RTC - real time clock
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///
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/// The RTC is and independent clock that keeps track of the date
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/// and time.
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2014-05-03 13:02:21 +01:00
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///
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/// Example usage:
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///
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/// rtc = pyb.RTC()
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/// rtc.datetime((2014, 5, 1, 4, 13, 0, 0, 0))
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/// print(rtc.datetime())
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2014-05-03 12:40:53 +01:00
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2014-04-19 02:17:30 +01:00
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RTC_HandleTypeDef RTCHandle;
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2014-03-15 12:54:48 +00:00
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2014-04-21 12:45:59 +01:00
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// rtc_info indicates various things about RTC startup
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// it's a bit of a hack at the moment
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2014-07-03 13:25:24 +01:00
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static mp_uint_t rtc_info;
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2014-03-15 12:54:48 +00:00
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// Note: LSI is around (32KHz), these dividers should work either way
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// ck_spre(1Hz) = RTCCLK(LSE) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)
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2015-11-07 11:03:12 +00:00
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// modify RTC_ASYNCH_PREDIV & RTC_SYNCH_PREDIV in board/<BN>/mpconfigport.h to change sub-second ticks
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2019-04-12 02:31:22 +01:00
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// default is 3906.25 us, min is ~30.52 us (will increase Ivbat by ~500nA)
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2015-11-07 11:03:12 +00:00
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#ifndef RTC_ASYNCH_PREDIV
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2014-03-15 12:54:48 +00:00
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#define RTC_ASYNCH_PREDIV (0x7f)
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2015-11-07 11:03:12 +00:00
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#endif
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#ifndef RTC_SYNCH_PREDIV
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2014-03-15 12:54:48 +00:00
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#define RTC_SYNCH_PREDIV (0x00ff)
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#endif
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2015-11-07 11:03:12 +00:00
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STATIC HAL_StatusTypeDef PYB_RTC_Init(RTC_HandleTypeDef *hrtc);
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2019-04-11 03:09:21 +01:00
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STATIC void PYB_RTC_MspInit_Kick(RTC_HandleTypeDef *hrtc, bool rtc_use_lse, bool rtc_use_byp);
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2015-11-07 11:03:12 +00:00
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STATIC HAL_StatusTypeDef PYB_RTC_MspInit_Finalise(RTC_HandleTypeDef *hrtc);
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2014-12-02 12:40:37 +00:00
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STATIC void RTC_CalendarConfig(void);
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2014-03-15 12:54:48 +00:00
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2019-04-11 03:09:21 +01:00
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#if MICROPY_HW_RTC_USE_LSE || MICROPY_HW_RTC_USE_BYPASS
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2015-11-01 13:31:44 +00:00
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STATIC bool rtc_use_lse = true;
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#else
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STATIC bool rtc_use_lse = false;
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#endif
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2015-11-07 11:03:12 +00:00
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STATIC uint32_t rtc_startup_tick;
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STATIC bool rtc_need_init_finalise = false;
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2015-11-01 13:31:44 +00:00
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2019-07-05 08:24:59 +01:00
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#if defined(STM32L0)
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#define BDCR CSR
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#define RCC_BDCR_RTCEN RCC_CSR_RTCEN
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#define RCC_BDCR_RTCSEL RCC_CSR_RTCSEL
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#define RCC_BDCR_RTCSEL_0 RCC_CSR_RTCSEL_0
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#define RCC_BDCR_RTCSEL_1 RCC_CSR_RTCSEL_1
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#define RCC_BDCR_LSEON RCC_CSR_LSEON
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#define RCC_BDCR_LSERDY RCC_CSR_LSERDY
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#define RCC_BDCR_LSEBYP RCC_CSR_LSEBYP
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#endif
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2015-12-04 12:05:05 +00:00
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void rtc_init_start(bool force_init) {
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2014-04-21 12:45:59 +01:00
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RTCHandle.Instance = RTC;
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2014-03-15 12:54:48 +00:00
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2014-04-21 12:45:59 +01:00
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/* Configure RTC prescaler and RTC data registers */
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/* RTC configured as follow:
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2014-03-15 12:54:48 +00:00
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- Hour Format = Format 24
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- Asynch Prediv = Value according to source clock
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- Synch Prediv = Value according to source clock
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- OutPut = Output Disable
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- OutPutPolarity = High Polarity
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2014-04-21 12:45:59 +01:00
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- OutPutType = Open Drain */
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RTCHandle.Init.HourFormat = RTC_HOURFORMAT_24;
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RTCHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
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RTCHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
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RTCHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
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RTCHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
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RTCHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
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2015-11-07 11:03:12 +00:00
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rtc_need_init_finalise = false;
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2015-12-04 12:05:05 +00:00
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if (!force_init) {
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2019-01-27 02:17:22 +00:00
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uint32_t bdcr = RCC->BDCR;
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if ((bdcr & (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL | RCC_BDCR_LSEON | RCC_BDCR_LSERDY))
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== (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL_0 | RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) {
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2015-12-04 12:05:05 +00:00
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// LSE is enabled & ready --> no need to (re-)init RTC
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// remove Backup Domain write protection
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HAL_PWR_EnableBkUpAccess();
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// Clear source Reset Flag
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__HAL_RCC_CLEAR_RESET_FLAGS();
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// provide some status information
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rtc_info |= 0x40000 | (RCC->BDCR & 7) | (RCC->CSR & 3) << 8;
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return;
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2019-01-27 02:17:22 +00:00
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} else if ((bdcr & (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL))
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2020-02-27 04:36:53 +00:00
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== (RCC_BDCR_RTCEN | RCC_BDCR_RTCSEL_1)) {
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2018-02-05 04:12:22 +00:00
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// LSI configured as the RTC clock source --> no need to (re-)init RTC
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2015-12-04 12:05:05 +00:00
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// remove Backup Domain write protection
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HAL_PWR_EnableBkUpAccess();
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// Clear source Reset Flag
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__HAL_RCC_CLEAR_RESET_FLAGS();
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2018-02-05 04:12:22 +00:00
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// Turn the LSI on (it may need this even if the RTC is running)
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RCC->CSR |= RCC_CSR_LSION;
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2015-12-04 12:05:05 +00:00
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// provide some status information
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rtc_info |= 0x80000 | (RCC->BDCR & 7) | (RCC->CSR & 3) << 8;
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return;
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}
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2015-10-27 10:55:47 +00:00
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}
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2015-12-04 12:05:05 +00:00
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2015-11-07 11:03:12 +00:00
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rtc_startup_tick = HAL_GetTick();
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rtc_info = 0x3f000000 | (rtc_startup_tick & 0xffffff);
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2019-04-11 03:09:21 +01:00
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PYB_RTC_MspInit_Kick(&RTCHandle, rtc_use_lse, MICROPY_HW_RTC_USE_BYPASS);
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2015-11-07 11:03:12 +00:00
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}
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2015-10-27 10:55:47 +00:00
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2015-11-07 11:03:12 +00:00
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void rtc_init_finalise() {
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if (!rtc_need_init_finalise) {
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return;
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}
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2014-03-15 12:54:48 +00:00
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2019-04-11 03:09:21 +01:00
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rtc_info = 0;
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while (PYB_RTC_Init(&RTCHandle) != HAL_OK) {
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2015-11-01 13:31:44 +00:00
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if (rtc_use_lse) {
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2019-04-11 03:09:21 +01:00
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#if MICROPY_HW_RTC_USE_BYPASS
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if (RCC->BDCR & RCC_BDCR_LSEBYP) {
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// LSEBYP failed, fallback to LSE non-bypass
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rtc_info |= 0x02000000;
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} else
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#endif
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{
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// LSE failed, fallback to LSI
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rtc_use_lse = false;
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rtc_info |= 0x01000000;
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}
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2015-11-07 11:03:12 +00:00
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rtc_startup_tick = HAL_GetTick();
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2019-04-11 03:09:21 +01:00
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PYB_RTC_MspInit_Kick(&RTCHandle, rtc_use_lse, false);
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2015-11-07 17:42:26 +00:00
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HAL_PWR_EnableBkUpAccess();
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2015-11-01 13:31:44 +00:00
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RTCHandle.State = HAL_RTC_STATE_RESET;
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} else {
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// init error
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2019-04-11 03:09:21 +01:00
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rtc_info |= 0xffff; // indicate error
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2015-11-01 13:31:44 +00:00
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return;
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}
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2014-04-21 12:45:59 +01:00
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}
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2019-04-11 03:09:21 +01:00
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// RTC started successfully
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rtc_info = 0x20000000;
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2018-02-05 03:40:06 +00:00
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// record if LSE or LSI is used
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rtc_info |= (rtc_use_lse << 28);
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2014-03-15 12:54:48 +00:00
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// record how long it took for the RTC to start up
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2015-11-07 11:03:12 +00:00
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rtc_info |= (HAL_GetTick() - rtc_startup_tick) & 0xffff;
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2014-03-15 12:54:48 +00:00
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2015-11-01 13:31:44 +00:00
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// fresh reset; configure RTC Calendar
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RTC_CalendarConfig();
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2019-07-17 07:33:31 +01:00
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#if defined(STM32L4) || defined(STM32WB)
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2020-02-27 04:36:53 +00:00
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if (__HAL_RCC_GET_FLAG(RCC_FLAG_BORRST) != RESET) {
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2016-03-22 15:56:28 +00:00
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#else
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2020-02-27 04:36:53 +00:00
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if (__HAL_RCC_GET_FLAG(RCC_FLAG_PORRST) != RESET) {
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#endif
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2015-11-01 13:31:44 +00:00
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// power on reset occurred
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rtc_info |= 0x10000;
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2014-03-15 12:54:48 +00:00
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}
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2020-02-27 04:36:53 +00:00
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if (__HAL_RCC_GET_FLAG(RCC_FLAG_PINRST) != RESET) {
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2015-11-01 13:31:44 +00:00
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// external reset occurred
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rtc_info |= 0x20000;
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}
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// Clear source Reset Flag
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__HAL_RCC_CLEAR_RESET_FLAGS();
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2015-11-07 11:03:12 +00:00
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rtc_need_init_finalise = false;
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2014-04-21 12:45:59 +01:00
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}
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2020-02-27 04:36:53 +00:00
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STATIC HAL_StatusTypeDef PYB_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
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2015-11-07 11:03:12 +00:00
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/*------------------------------ LSI Configuration -------------------------*/
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if ((RCC_OscInitStruct->OscillatorType & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) {
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// Check the LSI State
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if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) {
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// Enable the Internal Low Speed oscillator (LSI).
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__HAL_RCC_LSI_ENABLE();
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} else {
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// Disable the Internal Low Speed oscillator (LSI).
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__HAL_RCC_LSI_DISABLE();
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}
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2014-03-15 12:54:48 +00:00
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}
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2015-11-07 11:03:12 +00:00
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/*------------------------------ LSE Configuration -------------------------*/
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if ((RCC_OscInitStruct->OscillatorType & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) {
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2019-07-17 07:33:31 +01:00
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#if !defined(STM32H7) && !defined(STM32WB)
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2015-11-07 11:03:12 +00:00
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// Enable Power Clock
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2018-02-13 04:37:35 +00:00
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__HAL_RCC_PWR_CLK_ENABLE();
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2018-02-23 23:11:25 +00:00
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#endif
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// Enable access to the backup domain
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2015-11-07 11:03:12 +00:00
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HAL_PWR_EnableBkUpAccess();
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uint32_t tickstart = HAL_GetTick();
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2019-07-17 07:33:31 +01:00
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#if defined(STM32F7) || defined(STM32L4) || defined(STM32H7) || defined(STM32WB)
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2015-11-07 11:03:12 +00:00
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//__HAL_RCC_PWR_CLK_ENABLE();
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// Enable write access to Backup domain
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//PWR->CR1 |= PWR_CR1_DBP;
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// Wait for Backup domain Write protection disable
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while ((PWR->CR1 & PWR_CR1_DBP) == RESET) {
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if (HAL_GetTick() - tickstart > RCC_DBP_TIMEOUT_VALUE) {
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return HAL_TIMEOUT;
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}
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}
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#else
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// Enable write access to Backup domain
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//PWR->CR |= PWR_CR_DBP;
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// Wait for Backup domain Write protection disable
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while ((PWR->CR & PWR_CR_DBP) == RESET) {
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2018-02-13 04:37:35 +00:00
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if (HAL_GetTick() - tickstart > RCC_DBP_TIMEOUT_VALUE) {
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2015-11-07 11:03:12 +00:00
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return HAL_TIMEOUT;
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}
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}
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#endif
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2014-04-21 12:45:59 +01:00
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2019-04-11 03:09:21 +01:00
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#if MICROPY_HW_RTC_USE_BYPASS
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// If LSEBYP is enabled and new state is non-bypass then disable LSEBYP
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if (RCC_OscInitStruct->LSEState == RCC_LSE_ON && (RCC->BDCR & RCC_BDCR_LSEBYP)) {
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CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
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while (RCC->BDCR & RCC_BDCR_LSERDY) {
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}
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CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
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}
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#endif
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2015-11-07 11:03:12 +00:00
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// Set the new LSE configuration
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__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
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2014-04-21 12:45:59 +01:00
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}
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2015-11-07 11:03:12 +00:00
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return HAL_OK;
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2014-03-15 12:54:48 +00:00
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}
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2015-11-07 11:03:12 +00:00
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STATIC HAL_StatusTypeDef PYB_RTC_Init(RTC_HandleTypeDef *hrtc) {
|
|
|
|
// Check the RTC peripheral state
|
|
|
|
if (hrtc == NULL) {
|
|
|
|
return HAL_ERROR;
|
|
|
|
}
|
|
|
|
if (hrtc->State == HAL_RTC_STATE_RESET) {
|
|
|
|
// Allocate lock resource and initialize it
|
|
|
|
hrtc->Lock = HAL_UNLOCKED;
|
|
|
|
// Initialize RTC MSP
|
|
|
|
if (PYB_RTC_MspInit_Finalise(hrtc) != HAL_OK) {
|
|
|
|
return HAL_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set RTC state
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
|
|
|
|
|
|
// Disable the write protection for RTC registers
|
|
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
|
|
|
|
|
|
// Set Initialization mode
|
|
|
|
if (RTC_EnterInitMode(hrtc) != HAL_OK) {
|
|
|
|
// Enable the write protection for RTC registers
|
|
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
|
|
|
|
|
|
// Set RTC state
|
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
|
|
|
|
|
|
return HAL_ERROR;
|
|
|
|
} else {
|
|
|
|
// Clear RTC_CR FMT, OSEL and POL Bits
|
2020-02-27 04:36:53 +00:00
|
|
|
hrtc->Instance->CR &= ((uint32_t) ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
|
2015-11-07 11:03:12 +00:00
|
|
|
// Set RTC_CR register
|
|
|
|
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
|
|
|
|
|
|
|
|
// Configure the RTC PRER
|
|
|
|
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
|
|
|
|
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
|
|
|
|
|
|
|
|
// Exit Initialization mode
|
2020-02-27 04:36:53 +00:00
|
|
|
hrtc->Instance->ISR &= (uint32_t) ~RTC_ISR_INIT;
|
2015-11-07 11:03:12 +00:00
|
|
|
|
2019-07-17 07:33:31 +01:00
|
|
|
#if defined(STM32L0) || defined(STM32L4) || defined(STM32H7) || defined(STM32WB)
|
2020-02-27 04:36:53 +00:00
|
|
|
hrtc->Instance->OR &= (uint32_t) ~RTC_OR_ALARMOUTTYPE;
|
2016-03-22 15:56:28 +00:00
|
|
|
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
|
2018-03-16 23:42:50 +00:00
|
|
|
#elif defined(STM32F7)
|
2020-02-27 04:36:53 +00:00
|
|
|
hrtc->Instance->OR &= (uint32_t) ~RTC_OR_ALARMTYPE;
|
2015-11-07 11:03:12 +00:00
|
|
|
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
|
|
|
|
#else
|
2020-02-27 04:36:53 +00:00
|
|
|
hrtc->Instance->TAFCR &= (uint32_t) ~RTC_TAFCR_ALARMOUTTYPE;
|
2015-11-07 11:03:12 +00:00
|
|
|
hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// Enable the write protection for RTC registers
|
|
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
|
|
|
|
|
|
// Set RTC state
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
|
|
|
|
|
|
return HAL_OK;
|
|
|
|
}
|
|
|
|
}
|
2014-12-02 12:40:37 +00:00
|
|
|
|
2019-04-11 03:09:21 +01:00
|
|
|
STATIC void PYB_RTC_MspInit_Kick(RTC_HandleTypeDef *hrtc, bool rtc_use_lse, bool rtc_use_byp) {
|
2014-12-02 12:40:37 +00:00
|
|
|
/* To change the source clock of the RTC feature (LSE, LSI), You have to:
|
|
|
|
- Enable the power clock using __PWR_CLK_ENABLE()
|
|
|
|
- Enable write access using HAL_PWR_EnableBkUpAccess() function before to
|
|
|
|
configure the RTC clock source (to be done once after reset).
|
|
|
|
- Reset the Back up Domain using __HAL_RCC_BACKUPRESET_FORCE() and
|
|
|
|
__HAL_RCC_BACKUPRESET_RELEASE().
|
|
|
|
- Configure the needed RTc clock source */
|
|
|
|
|
2015-03-16 22:54:44 +00:00
|
|
|
// RTC clock source uses LSE (external crystal) only if relevant
|
|
|
|
// configuration variable is set. Otherwise it uses LSI (internal osc).
|
|
|
|
|
2015-11-07 11:03:12 +00:00
|
|
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
2020-02-27 04:36:53 +00:00
|
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
|
2014-12-02 12:40:37 +00:00
|
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
2019-04-11 03:09:21 +01:00
|
|
|
#if MICROPY_HW_RTC_USE_BYPASS
|
|
|
|
if (rtc_use_byp) {
|
2018-02-05 04:22:15 +00:00
|
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_BYPASS;
|
2019-04-11 03:09:21 +01:00
|
|
|
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
if (rtc_use_lse) {
|
2015-11-01 13:31:44 +00:00
|
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
|
|
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
|
|
|
|
} else {
|
|
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
|
|
|
|
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
|
|
|
}
|
2015-11-07 11:03:12 +00:00
|
|
|
PYB_RCC_OscConfig(&RCC_OscInitStruct);
|
|
|
|
|
|
|
|
// now ramp up osc. in background and flag calendear init needed
|
|
|
|
rtc_need_init_finalise = true;
|
|
|
|
}
|
|
|
|
|
2019-05-08 06:33:32 +01:00
|
|
|
#ifndef MICROPY_HW_RTC_LSE_TIMEOUT_MS
|
|
|
|
#define MICROPY_HW_RTC_LSE_TIMEOUT_MS 1000 // ST docs spec 2000 ms LSE startup, seems to be too pessimistic
|
|
|
|
#endif
|
|
|
|
#ifndef MICROPY_HW_RTC_LSI_TIMEOUT_MS
|
|
|
|
#define MICROPY_HW_RTC_LSI_TIMEOUT_MS 500 // this is way too pessimistic, typ. < 1ms
|
|
|
|
#endif
|
|
|
|
#ifndef MICROPY_HW_RTC_BYP_TIMEOUT_MS
|
|
|
|
#define MICROPY_HW_RTC_BYP_TIMEOUT_MS 150
|
|
|
|
#endif
|
2015-11-07 11:03:12 +00:00
|
|
|
|
|
|
|
STATIC HAL_StatusTypeDef PYB_RTC_MspInit_Finalise(RTC_HandleTypeDef *hrtc) {
|
|
|
|
// we already had a kick so now wait for the corresponding ready state...
|
|
|
|
if (rtc_use_lse) {
|
|
|
|
// we now have to wait for LSE ready or timeout
|
2019-05-08 06:33:32 +01:00
|
|
|
uint32_t timeout = MICROPY_HW_RTC_LSE_TIMEOUT_MS;
|
2019-04-11 03:09:21 +01:00
|
|
|
#if MICROPY_HW_RTC_USE_BYPASS
|
|
|
|
if (RCC->BDCR & RCC_BDCR_LSEBYP) {
|
2019-05-08 06:33:32 +01:00
|
|
|
timeout = MICROPY_HW_RTC_BYP_TIMEOUT_MS;
|
2019-04-11 03:09:21 +01:00
|
|
|
}
|
|
|
|
#endif
|
2015-11-07 11:03:12 +00:00
|
|
|
uint32_t tickstart = rtc_startup_tick;
|
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
|
2019-04-11 03:09:21 +01:00
|
|
|
if ((HAL_GetTick() - tickstart ) > timeout) {
|
2015-11-07 11:03:12 +00:00
|
|
|
return HAL_TIMEOUT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// we now have to wait for LSI ready or timeout
|
|
|
|
uint32_t tickstart = rtc_startup_tick;
|
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) {
|
2019-05-08 06:33:32 +01:00
|
|
|
if ((HAL_GetTick() - tickstart ) > MICROPY_HW_RTC_LSI_TIMEOUT_MS) {
|
2015-11-07 11:03:12 +00:00
|
|
|
return HAL_TIMEOUT;
|
|
|
|
}
|
|
|
|
}
|
2014-12-02 12:40:37 +00:00
|
|
|
}
|
|
|
|
|
2015-11-07 11:03:12 +00:00
|
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
2014-12-02 12:40:37 +00:00
|
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
2015-11-01 13:31:44 +00:00
|
|
|
if (rtc_use_lse) {
|
|
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
|
|
|
} else {
|
|
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
|
|
|
}
|
2014-12-02 12:40:37 +00:00
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
|
|
|
//Error_Handler();
|
2015-11-07 11:03:12 +00:00
|
|
|
return HAL_ERROR;
|
2014-12-02 12:40:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// enable RTC peripheral clock
|
|
|
|
__HAL_RCC_RTC_ENABLE();
|
2015-11-07 11:03:12 +00:00
|
|
|
return HAL_OK;
|
2014-12-02 12:40:37 +00:00
|
|
|
}
|
|
|
|
|
2015-11-07 11:03:12 +00:00
|
|
|
STATIC void RTC_CalendarConfig(void) {
|
|
|
|
// set the date to 1st Jan 2015
|
|
|
|
RTC_DateTypeDef date;
|
|
|
|
date.Year = 15;
|
|
|
|
date.Month = 1;
|
|
|
|
date.Date = 1;
|
|
|
|
date.WeekDay = RTC_WEEKDAY_THURSDAY;
|
|
|
|
|
2020-02-27 04:36:53 +00:00
|
|
|
if (HAL_RTC_SetDate(&RTCHandle, &date, RTC_FORMAT_BIN) != HAL_OK) {
|
2015-11-07 11:03:12 +00:00
|
|
|
// init error
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// set the time to 00:00:00
|
|
|
|
RTC_TimeTypeDef time;
|
|
|
|
time.Hours = 0;
|
|
|
|
time.Minutes = 0;
|
|
|
|
time.Seconds = 0;
|
|
|
|
time.TimeFormat = RTC_HOURFORMAT12_AM;
|
|
|
|
time.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
|
|
|
|
time.StoreOperation = RTC_STOREOPERATION_RESET;
|
|
|
|
|
2018-02-13 04:37:35 +00:00
|
|
|
if (HAL_RTC_SetTime(&RTCHandle, &time, RTC_FORMAT_BIN) != HAL_OK) {
|
2015-11-07 11:03:12 +00:00
|
|
|
// init error
|
|
|
|
return;
|
|
|
|
}
|
2014-12-02 12:40:37 +00:00
|
|
|
}
|
|
|
|
|
2014-03-15 12:54:48 +00:00
|
|
|
/******************************************************************************/
|
2017-06-30 08:22:17 +01:00
|
|
|
// MicroPython bindings
|
2014-03-15 12:54:48 +00:00
|
|
|
|
2014-04-19 02:17:30 +01:00
|
|
|
typedef struct _pyb_rtc_obj_t {
|
|
|
|
mp_obj_base_t base;
|
|
|
|
} pyb_rtc_obj_t;
|
2014-03-15 12:54:48 +00:00
|
|
|
|
2014-04-19 02:17:30 +01:00
|
|
|
STATIC const pyb_rtc_obj_t pyb_rtc_obj = {{&pyb_rtc_type}};
|
2014-03-15 12:54:48 +00:00
|
|
|
|
2014-05-03 12:40:53 +01:00
|
|
|
/// \classmethod \constructor()
|
|
|
|
/// Create an RTC object.
|
2017-01-04 13:10:42 +00:00
|
|
|
STATIC mp_obj_t pyb_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
|
2014-04-19 02:17:30 +01:00
|
|
|
// check arguments
|
2014-04-20 00:16:30 +01:00
|
|
|
mp_arg_check_num(n_args, n_kw, 0, 0, false);
|
2014-04-19 02:17:30 +01:00
|
|
|
|
|
|
|
// return constant object
|
2018-07-08 14:25:11 +01:00
|
|
|
return MP_OBJ_FROM_PTR(&pyb_rtc_obj);
|
2014-03-15 12:54:48 +00:00
|
|
|
}
|
|
|
|
|
2015-12-04 12:05:05 +00:00
|
|
|
// force rtc to re-initialise
|
|
|
|
mp_obj_t pyb_rtc_init(mp_obj_t self_in) {
|
|
|
|
rtc_init_start(true);
|
|
|
|
rtc_init_finalise();
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
MP_DEFINE_CONST_FUN_OBJ_1(pyb_rtc_init_obj, pyb_rtc_init);
|
|
|
|
|
2014-05-03 12:40:53 +01:00
|
|
|
/// \method info()
|
|
|
|
/// Get information about the startup time and reset source.
|
|
|
|
///
|
|
|
|
/// - The lower 0xffff are the number of milliseconds the RTC took to
|
|
|
|
/// start up.
|
|
|
|
/// - Bit 0x10000 is set if a power-on reset occurred.
|
|
|
|
/// - Bit 0x20000 is set if an external reset occurred
|
2014-04-19 02:17:30 +01:00
|
|
|
mp_obj_t pyb_rtc_info(mp_obj_t self_in) {
|
|
|
|
return mp_obj_new_int(rtc_info);
|
|
|
|
}
|
|
|
|
MP_DEFINE_CONST_FUN_OBJ_1(pyb_rtc_info_obj, pyb_rtc_info);
|
|
|
|
|
2014-05-03 12:40:53 +01:00
|
|
|
/// \method datetime([datetimetuple])
|
|
|
|
/// Get or set the date and time of the RTC.
|
|
|
|
///
|
|
|
|
/// With no arguments, this method returns an 8-tuple with the current
|
|
|
|
/// date and time. With 1 argument (being an 8-tuple) it sets the date
|
|
|
|
/// and time.
|
|
|
|
///
|
|
|
|
/// The 8-tuple has the following format:
|
|
|
|
///
|
|
|
|
/// (year, month, day, weekday, hours, minutes, seconds, subseconds)
|
|
|
|
///
|
|
|
|
/// `weekday` is 1-7 for Monday through Sunday.
|
|
|
|
///
|
2014-05-03 18:28:11 +01:00
|
|
|
/// `subseconds` counts down from 255 to 0
|
2015-11-07 11:03:12 +00:00
|
|
|
|
|
|
|
#define MEG_DIV_64 (1000000 / 64)
|
|
|
|
#define MEG_DIV_SCALE ((RTC_SYNCH_PREDIV + 1) / 64)
|
|
|
|
|
|
|
|
#if defined(MICROPY_HW_RTC_USE_US) && MICROPY_HW_RTC_USE_US
|
|
|
|
uint32_t rtc_subsec_to_us(uint32_t ss) {
|
|
|
|
return ((RTC_SYNCH_PREDIV - ss) * MEG_DIV_64) / MEG_DIV_SCALE;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t rtc_us_to_subsec(uint32_t us) {
|
|
|
|
return RTC_SYNCH_PREDIV - (us * MEG_DIV_SCALE / MEG_DIV_64);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define rtc_us_to_subsec
|
|
|
|
#define rtc_subsec_to_us
|
|
|
|
#endif
|
|
|
|
|
2017-08-30 01:59:58 +01:00
|
|
|
mp_obj_t pyb_rtc_datetime(size_t n_args, const mp_obj_t *args) {
|
2015-11-07 11:03:12 +00:00
|
|
|
rtc_init_finalise();
|
2014-04-19 02:17:30 +01:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get date and time
|
|
|
|
// note: need to call get time then get date to correctly access the registers
|
|
|
|
RTC_DateTypeDef date;
|
|
|
|
RTC_TimeTypeDef time;
|
2018-02-13 04:37:35 +00:00
|
|
|
HAL_RTC_GetTime(&RTCHandle, &time, RTC_FORMAT_BIN);
|
|
|
|
HAL_RTC_GetDate(&RTCHandle, &date, RTC_FORMAT_BIN);
|
2014-04-19 02:17:30 +01:00
|
|
|
mp_obj_t tuple[8] = {
|
|
|
|
mp_obj_new_int(2000 + date.Year),
|
|
|
|
mp_obj_new_int(date.Month),
|
|
|
|
mp_obj_new_int(date.Date),
|
|
|
|
mp_obj_new_int(date.WeekDay),
|
|
|
|
mp_obj_new_int(time.Hours),
|
|
|
|
mp_obj_new_int(time.Minutes),
|
|
|
|
mp_obj_new_int(time.Seconds),
|
2015-11-07 11:03:12 +00:00
|
|
|
mp_obj_new_int(rtc_subsec_to_us(time.SubSeconds)),
|
2014-04-19 02:17:30 +01:00
|
|
|
};
|
|
|
|
return mp_obj_new_tuple(8, tuple);
|
|
|
|
} else {
|
|
|
|
// set date and time
|
|
|
|
mp_obj_t *items;
|
|
|
|
mp_obj_get_array_fixed_n(args[1], 8, &items);
|
|
|
|
|
|
|
|
RTC_DateTypeDef date;
|
|
|
|
date.Year = mp_obj_get_int(items[0]) - 2000;
|
|
|
|
date.Month = mp_obj_get_int(items[1]);
|
|
|
|
date.Date = mp_obj_get_int(items[2]);
|
|
|
|
date.WeekDay = mp_obj_get_int(items[3]);
|
2018-02-13 04:37:35 +00:00
|
|
|
HAL_RTC_SetDate(&RTCHandle, &date, RTC_FORMAT_BIN);
|
2014-04-19 02:17:30 +01:00
|
|
|
|
|
|
|
RTC_TimeTypeDef time;
|
|
|
|
time.Hours = mp_obj_get_int(items[4]);
|
|
|
|
time.Minutes = mp_obj_get_int(items[5]);
|
|
|
|
time.Seconds = mp_obj_get_int(items[6]);
|
|
|
|
time.TimeFormat = RTC_HOURFORMAT12_AM;
|
|
|
|
time.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
|
|
|
|
time.StoreOperation = RTC_STOREOPERATION_SET;
|
2018-02-13 04:37:35 +00:00
|
|
|
HAL_RTC_SetTime(&RTCHandle, &time, RTC_FORMAT_BIN);
|
2014-04-19 02:17:30 +01:00
|
|
|
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_datetime_obj, 1, 2, pyb_rtc_datetime);
|
|
|
|
|
2019-07-05 08:24:59 +01:00
|
|
|
#if defined(STM32F0) || defined(STM32L0)
|
2018-05-28 09:10:53 +01:00
|
|
|
#define RTC_WKUP_IRQn RTC_IRQn
|
|
|
|
#endif
|
|
|
|
|
2015-03-15 17:15:55 +00:00
|
|
|
// wakeup(None)
|
|
|
|
// wakeup(ms, callback=None)
|
|
|
|
// wakeup(wucksel, wut, callback)
|
2017-08-30 01:59:58 +01:00
|
|
|
mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
|
2015-03-15 17:15:55 +00:00
|
|
|
// wut is wakeup counter start value, wucksel is clock source
|
|
|
|
// counter is decremented at wucksel rate, and wakes the MCU when it gets to 0
|
|
|
|
// wucksel=0b000 is RTC/16 (RTC runs at 32768Hz)
|
|
|
|
// wucksel=0b001 is RTC/8
|
|
|
|
// wucksel=0b010 is RTC/4
|
|
|
|
// wucksel=0b011 is RTC/2
|
|
|
|
// wucksel=0b100 is 1Hz clock
|
|
|
|
// wucksel=0b110 is 1Hz clock with 0x10000 added to wut
|
|
|
|
// so a 1 second wakeup could be wut=2047, wucksel=0b000, or wut=4095, wucksel=0b001, etc
|
|
|
|
|
2015-11-07 11:03:12 +00:00
|
|
|
rtc_init_finalise();
|
|
|
|
|
2015-03-15 17:15:55 +00:00
|
|
|
// disable wakeup IRQ while we configure it
|
|
|
|
HAL_NVIC_DisableIRQ(RTC_WKUP_IRQn);
|
|
|
|
|
|
|
|
bool enable = false;
|
|
|
|
mp_int_t wucksel;
|
|
|
|
mp_int_t wut;
|
|
|
|
mp_obj_t callback = mp_const_none;
|
|
|
|
if (n_args <= 3) {
|
|
|
|
if (args[1] == mp_const_none) {
|
|
|
|
// disable wakeup
|
|
|
|
} else {
|
|
|
|
// time given in ms
|
|
|
|
mp_int_t ms = mp_obj_get_int(args[1]);
|
|
|
|
mp_int_t div = 2;
|
|
|
|
wucksel = 3;
|
|
|
|
while (div <= 16 && ms > 2000 * div) {
|
|
|
|
div *= 2;
|
|
|
|
wucksel -= 1;
|
|
|
|
}
|
|
|
|
if (div <= 16) {
|
|
|
|
wut = 32768 / div * ms / 1000;
|
|
|
|
} else {
|
2015-10-08 12:41:12 +01:00
|
|
|
// use 1Hz clock
|
2015-03-15 17:15:55 +00:00
|
|
|
wucksel = 4;
|
|
|
|
wut = ms / 1000;
|
2015-10-08 12:41:12 +01:00
|
|
|
if (wut > 0x10000) {
|
|
|
|
// wut too large for 16-bit register, try to offset by 0x10000
|
|
|
|
wucksel = 6;
|
|
|
|
wut -= 0x10000;
|
|
|
|
if (wut > 0x10000) {
|
|
|
|
// wut still too large
|
2017-08-09 05:40:45 +01:00
|
|
|
mp_raise_ValueError("wakeup value too large");
|
2015-03-15 17:15:55 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2015-10-08 12:41:12 +01:00
|
|
|
// wut register should be 1 less than desired value, but guard against wut=0
|
|
|
|
if (wut > 0) {
|
|
|
|
wut -= 1;
|
|
|
|
}
|
2015-03-15 17:15:55 +00:00
|
|
|
enable = true;
|
|
|
|
}
|
|
|
|
if (n_args == 3) {
|
|
|
|
callback = args[2];
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// config values given directly
|
|
|
|
wucksel = mp_obj_get_int(args[1]);
|
|
|
|
wut = mp_obj_get_int(args[2]);
|
|
|
|
callback = args[3];
|
|
|
|
enable = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// set the callback
|
2018-07-31 08:24:10 +01:00
|
|
|
MP_STATE_PORT(pyb_extint_callback)[EXTI_RTC_WAKEUP] = callback;
|
2015-03-15 17:15:55 +00:00
|
|
|
|
|
|
|
// disable register write protection
|
|
|
|
RTC->WPR = 0xca;
|
|
|
|
RTC->WPR = 0x53;
|
|
|
|
|
|
|
|
// clear WUTE
|
2018-07-31 08:24:10 +01:00
|
|
|
RTC->CR &= ~RTC_CR_WUTE;
|
2015-03-15 17:15:55 +00:00
|
|
|
|
|
|
|
// wait until WUTWF is set
|
2018-07-31 08:24:10 +01:00
|
|
|
while (!(RTC->ISR & RTC_ISR_WUTWF)) {
|
2015-03-15 17:15:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
// program WUT
|
|
|
|
RTC->WUTR = wut;
|
|
|
|
|
|
|
|
// set WUTIE to enable wakeup interrupts
|
|
|
|
// set WUTE to enable wakeup
|
|
|
|
// program WUCKSEL
|
2015-10-06 23:39:57 +01:00
|
|
|
RTC->CR = (RTC->CR & ~7) | (1 << 14) | (1 << 10) | (wucksel & 7);
|
2015-03-15 17:15:55 +00:00
|
|
|
|
|
|
|
// enable register write protection
|
|
|
|
RTC->WPR = 0xff;
|
|
|
|
|
2018-07-31 08:24:10 +01:00
|
|
|
// enable external interrupts on line EXTI_RTC_WAKEUP
|
2019-07-17 07:33:31 +01:00
|
|
|
#if defined(STM32L4) || defined(STM32WB)
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI->IMR1 |= 1 << EXTI_RTC_WAKEUP;
|
|
|
|
EXTI->RTSR1 |= 1 << EXTI_RTC_WAKEUP;
|
2018-02-23 23:11:25 +00:00
|
|
|
#elif defined(STM32H7)
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI_D1->IMR1 |= 1 << EXTI_RTC_WAKEUP;
|
|
|
|
EXTI->RTSR1 |= 1 << EXTI_RTC_WAKEUP;
|
2016-03-22 15:56:28 +00:00
|
|
|
#else
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI->IMR |= 1 << EXTI_RTC_WAKEUP;
|
|
|
|
EXTI->RTSR |= 1 << EXTI_RTC_WAKEUP;
|
2016-03-22 15:56:28 +00:00
|
|
|
#endif
|
2015-03-15 17:15:55 +00:00
|
|
|
|
|
|
|
// clear interrupt flags
|
2018-07-31 08:24:10 +01:00
|
|
|
RTC->ISR &= ~RTC_ISR_WUTF;
|
2019-07-17 07:33:31 +01:00
|
|
|
#if defined(STM32L4) || defined(STM32WB)
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI->PR1 = 1 << EXTI_RTC_WAKEUP;
|
2018-02-23 23:11:25 +00:00
|
|
|
#elif defined(STM32H7)
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI_D1->PR1 = 1 << EXTI_RTC_WAKEUP;
|
2016-03-22 15:56:28 +00:00
|
|
|
#else
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI->PR = 1 << EXTI_RTC_WAKEUP;
|
2016-03-22 15:56:28 +00:00
|
|
|
#endif
|
2015-03-15 17:15:55 +00:00
|
|
|
|
2018-05-02 05:41:02 +01:00
|
|
|
NVIC_SetPriority(RTC_WKUP_IRQn, IRQ_PRI_RTC_WKUP);
|
2015-03-15 17:15:55 +00:00
|
|
|
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
|
|
|
|
|
|
|
|
//printf("wut=%d wucksel=%d\n", wut, wucksel);
|
|
|
|
} else {
|
|
|
|
// clear WUTIE to disable interrupts
|
2018-07-31 08:24:10 +01:00
|
|
|
RTC->CR &= ~RTC_CR_WUTIE;
|
2015-03-15 17:15:55 +00:00
|
|
|
|
|
|
|
// enable register write protection
|
|
|
|
RTC->WPR = 0xff;
|
|
|
|
|
2018-07-31 08:24:10 +01:00
|
|
|
// disable external interrupts on line EXTI_RTC_WAKEUP
|
2019-07-17 07:33:31 +01:00
|
|
|
#if defined(STM32L4) || defined(STM32WB)
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI->IMR1 &= ~(1 << EXTI_RTC_WAKEUP);
|
2018-02-23 23:11:25 +00:00
|
|
|
#elif defined(STM32H7)
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI_D1->IMR1 |= 1 << EXTI_RTC_WAKEUP;
|
2016-03-22 15:56:28 +00:00
|
|
|
#else
|
2018-07-31 08:24:10 +01:00
|
|
|
EXTI->IMR &= ~(1 << EXTI_RTC_WAKEUP);
|
2016-03-22 15:56:28 +00:00
|
|
|
#endif
|
2015-03-15 17:15:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_wakeup_obj, 2, 4, pyb_rtc_wakeup);
|
|
|
|
|
2015-05-07 18:18:52 +01:00
|
|
|
// calibration(None)
|
|
|
|
// calibration(cal)
|
|
|
|
// When an integer argument is provided, check that it falls in the range [-511 to 512]
|
|
|
|
// and set the calibration value; otherwise return calibration value
|
2017-08-30 01:59:58 +01:00
|
|
|
mp_obj_t pyb_rtc_calibration(size_t n_args, const mp_obj_t *args) {
|
2015-11-07 11:03:12 +00:00
|
|
|
rtc_init_finalise();
|
2015-05-07 18:18:52 +01:00
|
|
|
mp_int_t cal;
|
|
|
|
if (n_args == 2) {
|
2015-10-20 12:04:37 +01:00
|
|
|
cal = mp_obj_get_int(args[1]);
|
|
|
|
mp_uint_t cal_p, cal_m;
|
|
|
|
if (cal < -511 || cal > 512) {
|
2020-02-27 04:36:53 +00:00
|
|
|
#if defined(MICROPY_HW_RTC_USE_CALOUT) && MICROPY_HW_RTC_USE_CALOUT
|
2015-11-07 11:03:12 +00:00
|
|
|
if ((cal & 0xfffe) == 0x0ffe) {
|
|
|
|
// turn on/off X18 (PC13) 512Hz output
|
|
|
|
// Note:
|
|
|
|
// Output will stay active even in VBAT mode (and inrease current)
|
|
|
|
if (cal & 1) {
|
|
|
|
HAL_RTCEx_SetCalibrationOutPut(&RTCHandle, RTC_CALIBOUTPUT_512HZ);
|
|
|
|
} else {
|
|
|
|
HAL_RTCEx_DeactivateCalibrationOutPut(&RTCHandle);
|
|
|
|
}
|
|
|
|
return mp_obj_new_int(cal & 1);
|
|
|
|
} else {
|
2017-08-09 05:40:45 +01:00
|
|
|
mp_raise_ValueError("calibration value out of range");
|
2015-11-07 11:03:12 +00:00
|
|
|
}
|
2020-02-27 04:36:53 +00:00
|
|
|
#else
|
2017-08-09 05:40:45 +01:00
|
|
|
mp_raise_ValueError("calibration value out of range");
|
2020-02-27 04:36:53 +00:00
|
|
|
#endif
|
2015-10-20 12:04:37 +01:00
|
|
|
}
|
|
|
|
if (cal > 0) {
|
|
|
|
cal_p = RTC_SMOOTHCALIB_PLUSPULSES_SET;
|
|
|
|
cal_m = 512 - cal;
|
|
|
|
} else {
|
|
|
|
cal_p = RTC_SMOOTHCALIB_PLUSPULSES_RESET;
|
|
|
|
cal_m = -cal;
|
|
|
|
}
|
|
|
|
HAL_RTCEx_SetSmoothCalib(&RTCHandle, RTC_SMOOTHCALIB_PERIOD_32SEC, cal_p, cal_m);
|
|
|
|
return mp_const_none;
|
2015-05-07 18:18:52 +01:00
|
|
|
} else {
|
|
|
|
// printf("CALR = 0x%x\n", (mp_uint_t) RTCHandle.Instance->CALR); // DEBUG
|
2015-10-20 12:04:37 +01:00
|
|
|
// Test if CALP bit is set in CALR:
|
|
|
|
if (RTCHandle.Instance->CALR & 0x8000) {
|
|
|
|
cal = 512 - (RTCHandle.Instance->CALR & 0x1ff);
|
|
|
|
} else {
|
|
|
|
cal = -(RTCHandle.Instance->CALR & 0x1ff);
|
|
|
|
}
|
|
|
|
return mp_obj_new_int(cal);
|
2015-05-07 18:18:52 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_calibration_obj, 1, 2, pyb_rtc_calibration);
|
2015-10-20 12:04:37 +01:00
|
|
|
|
2017-05-06 08:03:40 +01:00
|
|
|
STATIC const mp_rom_map_elem_t pyb_rtc_locals_dict_table[] = {
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_rtc_init_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_info), MP_ROM_PTR(&pyb_rtc_info_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_datetime), MP_ROM_PTR(&pyb_rtc_datetime_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_wakeup), MP_ROM_PTR(&pyb_rtc_wakeup_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_calibration), MP_ROM_PTR(&pyb_rtc_calibration_obj) },
|
2014-04-19 02:17:30 +01:00
|
|
|
};
|
|
|
|
STATIC MP_DEFINE_CONST_DICT(pyb_rtc_locals_dict, pyb_rtc_locals_dict_table);
|
|
|
|
|
|
|
|
const mp_obj_type_t pyb_rtc_type = {
|
|
|
|
{ &mp_type_type },
|
|
|
|
.name = MP_QSTR_RTC,
|
|
|
|
.make_new = pyb_rtc_make_new,
|
2020-02-27 04:36:53 +00:00
|
|
|
.locals_dict = (mp_obj_dict_t *)&pyb_rtc_locals_dict,
|
2014-04-19 02:17:30 +01:00
|
|
|
};
|