2021-01-20 13:34:08 +00:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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2023-10-10 13:46:07 +01:00
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* Copyright (c) 2020-2023 Damien P. George
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2021-01-20 13:34:08 +00:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2023-10-10 13:46:07 +01:00
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// This file is never compiled standalone, it's included directly from
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// extmod/machine_uart.c via MICROPY_PY_MACHINE_UART_INCLUDEFILE.
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2021-01-20 13:34:08 +00:00
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#include "py/mphal.h"
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#include "py/mperrno.h"
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2021-03-11 07:36:16 +00:00
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#include "py/ringbuf.h"
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2021-01-20 13:34:08 +00:00
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2021-03-11 07:36:16 +00:00
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#include "hardware/irq.h"
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2021-01-20 13:34:08 +00:00
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#include "hardware/uart.h"
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2021-03-11 07:36:16 +00:00
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#include "hardware/regs/uart.h"
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2022-03-02 09:19:45 +00:00
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#include "pico/mutex.h"
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2021-01-20 13:34:08 +00:00
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#define DEFAULT_UART_BAUDRATE (115200)
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#define DEFAULT_UART_BITS (8)
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#define DEFAULT_UART_STOP (1)
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2021-07-07 22:56:29 +01:00
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2023-04-04 17:23:22 +01:00
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#ifdef MICROPY_HW_UART_NO_DEFAULT_PINS
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// With no default I2C, need to require the pin args.
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#define MICROPY_UART_PINS_ARG_OPTS MP_ARG_REQUIRED
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#else
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// Most boards do not require pin args.
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#define MICROPY_UART_PINS_ARG_OPTS 0
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#endif
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2021-07-07 22:56:29 +01:00
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// UART 0 default pins
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#if !defined(MICROPY_HW_UART0_TX)
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#define MICROPY_HW_UART0_TX (0)
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#define MICROPY_HW_UART0_RX (1)
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#define MICROPY_HW_UART0_CTS (2)
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#define MICROPY_HW_UART0_RTS (3)
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#endif
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// UART 1 default pins
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#if !defined(MICROPY_HW_UART1_TX)
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#define MICROPY_HW_UART1_TX (4)
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#define MICROPY_HW_UART1_RX (5)
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#define MICROPY_HW_UART1_CTS (6)
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#define MICROPY_HW_UART1_RTS (7)
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#endif
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2021-03-11 07:36:16 +00:00
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#define DEFAULT_BUFFER_SIZE (256)
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#define MIN_BUFFER_SIZE (32)
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#define MAX_BUFFER_SIZE (32766)
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2021-01-20 13:34:08 +00:00
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#define IS_VALID_PERIPH(uart, pin) (((((pin) + 4) & 8) >> 3) == (uart))
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#define IS_VALID_TX(uart, pin) (((pin) & 3) == 0 && IS_VALID_PERIPH(uart, pin))
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#define IS_VALID_RX(uart, pin) (((pin) & 3) == 1 && IS_VALID_PERIPH(uart, pin))
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2021-07-07 22:47:20 +01:00
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#define IS_VALID_CTS(uart, pin) (((pin) & 3) == 2 && IS_VALID_PERIPH(uart, pin))
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#define IS_VALID_RTS(uart, pin) (((pin) & 3) == 3 && IS_VALID_PERIPH(uart, pin))
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2021-01-20 13:34:08 +00:00
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2021-02-10 13:07:18 +00:00
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#define UART_INVERT_TX (1)
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#define UART_INVERT_RX (2)
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#define UART_INVERT_MASK (UART_INVERT_TX | UART_INVERT_RX)
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2021-07-07 22:47:20 +01:00
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#define UART_HWCONTROL_CTS (1)
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#define UART_HWCONTROL_RTS (2)
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2022-03-02 09:19:45 +00:00
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STATIC mutex_t write_mutex_0;
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STATIC mutex_t write_mutex_1;
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STATIC mutex_t read_mutex_0;
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STATIC mutex_t read_mutex_1;
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auto_init_mutex(write_mutex_0);
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auto_init_mutex(write_mutex_1);
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auto_init_mutex(read_mutex_0);
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auto_init_mutex(read_mutex_1);
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2021-01-20 13:34:08 +00:00
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typedef struct _machine_uart_obj_t {
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mp_obj_base_t base;
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uart_inst_t *const uart;
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uint8_t uart_id;
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uint32_t baudrate;
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uint8_t bits;
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uart_parity_t parity;
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uint8_t stop;
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uint8_t tx;
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uint8_t rx;
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2021-07-07 22:47:20 +01:00
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uint8_t cts;
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uint8_t rts;
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2021-02-09 14:50:21 +00:00
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uint16_t timeout; // timeout waiting for first char (in ms)
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uint16_t timeout_char; // timeout waiting between chars (in ms)
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2021-02-10 13:07:18 +00:00
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uint8_t invert;
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2021-07-07 22:47:20 +01:00
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uint8_t flow;
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2021-03-11 07:36:16 +00:00
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ringbuf_t read_buffer;
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2022-03-02 09:19:45 +00:00
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mutex_t *read_mutex;
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2021-03-11 07:36:16 +00:00
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ringbuf_t write_buffer;
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2022-03-02 09:19:45 +00:00
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mutex_t *write_mutex;
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2021-01-20 13:34:08 +00:00
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} machine_uart_obj_t;
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STATIC machine_uart_obj_t machine_uart_obj[] = {
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2021-03-11 07:36:16 +00:00
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{{&machine_uart_type}, uart0, 0, 0, DEFAULT_UART_BITS, UART_PARITY_NONE, DEFAULT_UART_STOP,
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2021-07-07 22:56:29 +01:00
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MICROPY_HW_UART0_TX, MICROPY_HW_UART0_RX, MICROPY_HW_UART0_CTS, MICROPY_HW_UART0_RTS,
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2022-03-02 09:19:45 +00:00
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0, 0, 0, 0, {NULL, 1, 0, 0}, &read_mutex_0, {NULL, 1, 0, 0}, &write_mutex_0},
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2021-03-11 07:36:16 +00:00
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{{&machine_uart_type}, uart1, 1, 0, DEFAULT_UART_BITS, UART_PARITY_NONE, DEFAULT_UART_STOP,
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2021-07-07 22:56:29 +01:00
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MICROPY_HW_UART1_TX, MICROPY_HW_UART1_RX, MICROPY_HW_UART1_CTS, MICROPY_HW_UART1_RTS,
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2022-03-02 09:19:45 +00:00
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0, 0, 0, 0, {NULL, 1, 0, 0}, &read_mutex_1, {NULL, 1, 0, 0}, &write_mutex_1},
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2021-01-20 13:34:08 +00:00
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};
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STATIC const char *_parity_name[] = {"None", "0", "1"};
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2021-02-10 13:07:18 +00:00
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STATIC const char *_invert_name[] = {"None", "INV_TX", "INV_RX", "INV_TX|INV_RX"};
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2021-01-20 13:34:08 +00:00
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2021-03-11 07:36:16 +00:00
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/******************************************************************************/
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// IRQ and buffer handling
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2022-03-02 09:19:45 +00:00
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static inline bool write_mutex_try_lock(machine_uart_obj_t *u) {
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return mutex_enter_timeout_ms(u->write_mutex, 0);
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}
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static inline void write_mutex_unlock(machine_uart_obj_t *u) {
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mutex_exit(u->write_mutex);
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}
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static inline bool read_mutex_try_lock(machine_uart_obj_t *u) {
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return mutex_enter_timeout_ms(u->read_mutex, 0);
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}
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static inline void read_mutex_unlock(machine_uart_obj_t *u) {
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mutex_exit(u->read_mutex);
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}
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2022-02-03 13:41:45 +00:00
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// take all bytes from the fifo and store them in the buffer
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2021-03-11 07:36:16 +00:00
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STATIC void uart_drain_rx_fifo(machine_uart_obj_t *self) {
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2022-03-02 09:19:45 +00:00
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if (read_mutex_try_lock(self)) {
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while (uart_is_readable(self->uart) && ringbuf_free(&self->read_buffer) > 0) {
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2023-10-24 09:16:00 +01:00
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// Get a byte from uart and put into the buffer. Every entry from
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// the FIFO is accompanied by 4 error bits, that may be used for
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// error handling.
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uint16_t c = uart_get_hw(self->uart)->dr;
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if (c & UART_UARTDR_OE_BITS) {
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// Overrun Error: We missed at least one byte. Not much we can do here.
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}
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if (c & UART_UARTDR_BE_BITS) {
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// Break Error: RX was held low for longer than one character
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// (11 bits). We did *not* read the zero byte that we seemed to
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// read from dr.
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continue;
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}
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if (c & UART_UARTDR_PE_BITS) {
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// Parity Error: The byte we read is invalid.
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}
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if (c & UART_UARTDR_FE_BITS) {
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// Framing Error: We did not receive a valid stop bit.
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}
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ringbuf_put(&(self->read_buffer), c);
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2022-03-02 09:19:45 +00:00
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}
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read_mutex_unlock(self);
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2021-03-11 07:36:16 +00:00
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}
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}
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// take bytes from the buffer and put them into the UART FIFO
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2022-03-02 09:19:45 +00:00
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// Re-entrancy: quit if an instance already running
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2021-03-11 07:36:16 +00:00
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STATIC void uart_fill_tx_fifo(machine_uart_obj_t *self) {
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2022-03-02 09:19:45 +00:00
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if (write_mutex_try_lock(self)) {
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while (uart_is_writable(self->uart) && ringbuf_avail(&self->write_buffer) > 0) {
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// get a byte from the buffer and put it into the uart
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uart_get_hw(self->uart)->dr = ringbuf_get(&(self->write_buffer));
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}
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write_mutex_unlock(self);
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2021-03-11 07:36:16 +00:00
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}
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}
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STATIC inline void uart_service_interrupt(machine_uart_obj_t *self) {
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2021-12-09 23:27:45 +00:00
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if (uart_get_hw(self->uart)->mis & (UART_UARTMIS_RXMIS_BITS | UART_UARTMIS_RTMIS_BITS)) { // rx interrupt?
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2021-03-11 07:36:16 +00:00
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// clear all interrupt bits but tx
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uart_get_hw(self->uart)->icr = UART_UARTICR_BITS & (~UART_UARTICR_TXIC_BITS);
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2022-03-02 09:19:45 +00:00
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uart_drain_rx_fifo(self);
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2021-03-11 07:36:16 +00:00
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}
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if (uart_get_hw(self->uart)->mis & UART_UARTMIS_TXMIS_BITS) { // tx interrupt?
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// clear all interrupt bits but rx
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uart_get_hw(self->uart)->icr = UART_UARTICR_BITS & (~UART_UARTICR_RXIC_BITS);
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2022-03-02 09:19:45 +00:00
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uart_fill_tx_fifo(self);
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2021-03-11 07:36:16 +00:00
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}
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}
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STATIC void uart0_irq_handler(void) {
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uart_service_interrupt(&machine_uart_obj[0]);
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}
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STATIC void uart1_irq_handler(void) {
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uart_service_interrupt(&machine_uart_obj[1]);
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}
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2021-01-20 13:34:08 +00:00
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/******************************************************************************/
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// MicroPython bindings for UART
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2023-10-10 13:46:07 +01:00
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#define MICROPY_PY_MACHINE_UART_CLASS_CONSTANTS \
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{ MP_ROM_QSTR(MP_QSTR_INV_TX), MP_ROM_INT(UART_INVERT_TX) }, \
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{ MP_ROM_QSTR(MP_QSTR_INV_RX), MP_ROM_INT(UART_INVERT_RX) }, \
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{ MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_HWCONTROL_CTS) }, \
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{ MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_HWCONTROL_RTS) }, \
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STATIC void mp_machine_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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2021-01-20 13:34:08 +00:00
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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2021-03-11 07:36:16 +00:00
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mp_printf(print, "UART(%u, baudrate=%u, bits=%u, parity=%s, stop=%u, tx=%d, rx=%d, "
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"txbuf=%d, rxbuf=%d, timeout=%u, timeout_char=%u, invert=%s)",
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2021-01-20 13:34:08 +00:00
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self->uart_id, self->baudrate, self->bits, _parity_name[self->parity],
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2021-03-11 07:36:16 +00:00
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self->stop, self->tx, self->rx, self->write_buffer.size - 1, self->read_buffer.size - 1,
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self->timeout, self->timeout_char, _invert_name[self->invert]);
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2021-01-20 13:34:08 +00:00
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}
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2023-10-10 13:46:07 +01:00
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STATIC void mp_machine_uart_init_helper(machine_uart_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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2022-01-20 18:45:31 +00:00
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enum { ARG_baudrate, ARG_bits, ARG_parity, ARG_stop, ARG_tx, ARG_rx, ARG_cts, ARG_rts,
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2021-07-07 22:47:20 +01:00
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ARG_timeout, ARG_timeout_char, ARG_invert, ARG_flow, ARG_txbuf, ARG_rxbuf};
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2021-01-20 13:34:08 +00:00
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_bits, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_parity, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_INT(-1)} },
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{ MP_QSTR_stop, MP_ARG_INT, {.u_int = -1} },
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2023-04-04 17:23:22 +01:00
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{ MP_QSTR_tx, MICROPY_UART_PINS_ARG_OPTS | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_rx, MICROPY_UART_PINS_ARG_OPTS | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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2021-07-07 22:47:20 +01:00
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{ MP_QSTR_cts, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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{ MP_QSTR_rts, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
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2021-02-09 14:50:21 +00:00
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{ MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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2021-02-10 13:07:18 +00:00
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{ MP_QSTR_invert, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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2021-07-07 22:47:20 +01:00
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{ MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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2021-03-11 07:36:16 +00:00
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{ MP_QSTR_txbuf, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_rxbuf, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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2021-01-20 13:34:08 +00:00
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};
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// Parse args.
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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2022-01-20 18:45:31 +00:00
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mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
|
2021-01-20 13:34:08 +00:00
|
|
|
|
|
|
|
// Set baudrate if configured.
|
|
|
|
if (args[ARG_baudrate].u_int > 0) {
|
|
|
|
self->baudrate = args[ARG_baudrate].u_int;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set bits if configured.
|
|
|
|
if (args[ARG_bits].u_int > 0) {
|
|
|
|
self->bits = args[ARG_bits].u_int;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set parity if configured.
|
|
|
|
if (args[ARG_parity].u_obj != MP_OBJ_NEW_SMALL_INT(-1)) {
|
|
|
|
if (args[ARG_parity].u_obj == mp_const_none) {
|
|
|
|
self->parity = UART_PARITY_NONE;
|
|
|
|
} else if (mp_obj_get_int(args[ARG_parity].u_obj) & 1) {
|
|
|
|
self->parity = UART_PARITY_ODD;
|
|
|
|
} else {
|
|
|
|
self->parity = UART_PARITY_EVEN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set stop bits if configured.
|
|
|
|
if (args[ARG_stop].u_int > 0) {
|
|
|
|
self->stop = args[ARG_stop].u_int;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set TX/RX pins if configured.
|
|
|
|
if (args[ARG_tx].u_obj != mp_const_none) {
|
|
|
|
int tx = mp_hal_get_pin_obj(args[ARG_tx].u_obj);
|
|
|
|
if (!IS_VALID_TX(self->uart_id, tx)) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("bad TX pin"));
|
|
|
|
}
|
|
|
|
self->tx = tx;
|
|
|
|
}
|
|
|
|
if (args[ARG_rx].u_obj != mp_const_none) {
|
|
|
|
int rx = mp_hal_get_pin_obj(args[ARG_rx].u_obj);
|
|
|
|
if (!IS_VALID_RX(self->uart_id, rx)) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("bad RX pin"));
|
|
|
|
}
|
|
|
|
self->rx = rx;
|
|
|
|
}
|
|
|
|
|
2021-07-07 22:47:20 +01:00
|
|
|
// Set CTS/RTS pins if configured.
|
|
|
|
if (args[ARG_cts].u_obj != mp_const_none) {
|
|
|
|
int cts = mp_hal_get_pin_obj(args[ARG_cts].u_obj);
|
|
|
|
if (!IS_VALID_CTS(self->uart_id, cts)) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("bad CTS pin"));
|
|
|
|
}
|
|
|
|
self->cts = cts;
|
|
|
|
}
|
|
|
|
if (args[ARG_rts].u_obj != mp_const_none) {
|
|
|
|
int rts = mp_hal_get_pin_obj(args[ARG_rts].u_obj);
|
|
|
|
if (!IS_VALID_RTS(self->uart_id, rts)) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("bad RTS pin"));
|
|
|
|
}
|
|
|
|
self->rts = rts;
|
|
|
|
}
|
|
|
|
|
2021-02-09 14:50:21 +00:00
|
|
|
// Set timeout if configured.
|
|
|
|
if (args[ARG_timeout].u_int >= 0) {
|
|
|
|
self->timeout = args[ARG_timeout].u_int;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set timeout_char if configured.
|
|
|
|
if (args[ARG_timeout_char].u_int >= 0) {
|
|
|
|
self->timeout_char = args[ARG_timeout_char].u_int;
|
|
|
|
}
|
|
|
|
|
2021-02-10 13:07:18 +00:00
|
|
|
// Set line inversion if configured.
|
|
|
|
if (args[ARG_invert].u_int >= 0) {
|
|
|
|
if (args[ARG_invert].u_int & ~UART_INVERT_MASK) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("bad inversion mask"));
|
|
|
|
}
|
|
|
|
self->invert = args[ARG_invert].u_int;
|
|
|
|
}
|
|
|
|
|
2021-07-07 22:47:20 +01:00
|
|
|
// Set hardware flow control if configured.
|
|
|
|
if (args[ARG_flow].u_int >= 0) {
|
|
|
|
if (args[ARG_flow].u_int & ~(UART_HWCONTROL_CTS | UART_HWCONTROL_RTS)) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("bad hardware flow control mask"));
|
|
|
|
}
|
|
|
|
self->flow = args[ARG_flow].u_int;
|
|
|
|
}
|
|
|
|
|
2021-03-11 07:36:16 +00:00
|
|
|
// Set the RX buffer size if configured.
|
|
|
|
size_t rxbuf_len = DEFAULT_BUFFER_SIZE;
|
|
|
|
if (args[ARG_rxbuf].u_int > 0) {
|
|
|
|
rxbuf_len = args[ARG_rxbuf].u_int;
|
|
|
|
if (rxbuf_len < MIN_BUFFER_SIZE) {
|
|
|
|
rxbuf_len = MIN_BUFFER_SIZE;
|
|
|
|
} else if (rxbuf_len > MAX_BUFFER_SIZE) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("rxbuf too large"));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set the TX buffer size if configured.
|
|
|
|
size_t txbuf_len = DEFAULT_BUFFER_SIZE;
|
|
|
|
if (args[ARG_txbuf].u_int > 0) {
|
|
|
|
txbuf_len = args[ARG_txbuf].u_int;
|
|
|
|
if (txbuf_len < MIN_BUFFER_SIZE) {
|
|
|
|
txbuf_len = MIN_BUFFER_SIZE;
|
|
|
|
} else if (txbuf_len > MAX_BUFFER_SIZE) {
|
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("txbuf too large"));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-01-20 13:34:08 +00:00
|
|
|
// Initialise the UART peripheral if any arguments given, or it was not initialised previously.
|
2022-01-20 18:45:31 +00:00
|
|
|
if (n_args > 0 || kw_args->used > 0 || self->baudrate == 0) {
|
2021-01-20 13:34:08 +00:00
|
|
|
if (self->baudrate == 0) {
|
|
|
|
self->baudrate = DEFAULT_UART_BAUDRATE;
|
|
|
|
}
|
2021-02-09 14:50:21 +00:00
|
|
|
|
|
|
|
// Make sure timeout_char is at least as long as a whole character (13 bits to be safe).
|
|
|
|
uint32_t min_timeout_char = 13000 / self->baudrate + 1;
|
|
|
|
if (self->timeout_char < min_timeout_char) {
|
|
|
|
self->timeout_char = min_timeout_char;
|
|
|
|
}
|
|
|
|
|
2021-01-20 13:34:08 +00:00
|
|
|
uart_init(self->uart, self->baudrate);
|
|
|
|
uart_set_format(self->uart, self->bits, self->stop, self->parity);
|
2023-03-08 19:59:24 +00:00
|
|
|
__DSB(); // make sure UARTLCR_H register is written to
|
2021-01-20 13:34:08 +00:00
|
|
|
uart_set_fifo_enabled(self->uart, true);
|
2023-03-08 19:59:24 +00:00
|
|
|
__DSB(); // make sure UARTLCR_H register is written to
|
2021-01-20 13:34:08 +00:00
|
|
|
gpio_set_function(self->tx, GPIO_FUNC_UART);
|
|
|
|
gpio_set_function(self->rx, GPIO_FUNC_UART);
|
2021-02-10 13:07:18 +00:00
|
|
|
if (self->invert & UART_INVERT_RX) {
|
|
|
|
gpio_set_inover(self->rx, GPIO_OVERRIDE_INVERT);
|
|
|
|
}
|
|
|
|
if (self->invert & UART_INVERT_TX) {
|
|
|
|
gpio_set_outover(self->tx, GPIO_OVERRIDE_INVERT);
|
|
|
|
}
|
2021-03-11 07:36:16 +00:00
|
|
|
|
2021-07-07 22:47:20 +01:00
|
|
|
// Set hardware flow control if configured.
|
|
|
|
if (self->flow & UART_HWCONTROL_CTS) {
|
|
|
|
gpio_set_function(self->cts, GPIO_FUNC_UART);
|
|
|
|
}
|
|
|
|
if (self->flow & UART_HWCONTROL_RTS) {
|
|
|
|
gpio_set_function(self->rts, GPIO_FUNC_UART);
|
|
|
|
}
|
|
|
|
uart_set_hw_flow(self->uart, self->flow & UART_HWCONTROL_CTS, self->flow & UART_HWCONTROL_RTS);
|
|
|
|
|
2021-03-11 07:36:16 +00:00
|
|
|
// Allocate the RX/TX buffers.
|
|
|
|
ringbuf_alloc(&(self->read_buffer), rxbuf_len + 1);
|
2022-01-20 18:45:31 +00:00
|
|
|
MP_STATE_PORT(rp2_uart_rx_buffer[self->uart_id]) = self->read_buffer.buf;
|
2021-03-11 07:36:16 +00:00
|
|
|
|
|
|
|
ringbuf_alloc(&(self->write_buffer), txbuf_len + 1);
|
2022-01-20 18:45:31 +00:00
|
|
|
MP_STATE_PORT(rp2_uart_tx_buffer[self->uart_id]) = self->write_buffer.buf;
|
2021-03-11 07:36:16 +00:00
|
|
|
|
|
|
|
// Set the irq handler.
|
|
|
|
if (self->uart_id == 0) {
|
|
|
|
irq_set_exclusive_handler(UART0_IRQ, uart0_irq_handler);
|
|
|
|
irq_set_enabled(UART0_IRQ, true);
|
|
|
|
} else {
|
|
|
|
irq_set_exclusive_handler(UART1_IRQ, uart1_irq_handler);
|
|
|
|
irq_set_enabled(UART1_IRQ, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Enable the uart irq; this macro sets the rx irq level to 4.
|
|
|
|
uart_set_irq_enables(self->uart, true, true);
|
2021-01-20 13:34:08 +00:00
|
|
|
}
|
2022-01-20 18:45:31 +00:00
|
|
|
}
|
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC mp_obj_t mp_machine_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
|
2022-01-20 18:45:31 +00:00
|
|
|
mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
|
|
|
|
|
|
|
|
// Get UART bus.
|
|
|
|
int uart_id = mp_obj_get_int(args[0]);
|
|
|
|
if (uart_id < 0 || uart_id >= MP_ARRAY_SIZE(machine_uart_obj)) {
|
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%d) doesn't exist"), uart_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get static peripheral object.
|
|
|
|
machine_uart_obj_t *self = (machine_uart_obj_t *)&machine_uart_obj[uart_id];
|
|
|
|
|
|
|
|
// Initialise the UART peripheral.
|
|
|
|
mp_map_t kw_args;
|
|
|
|
mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
|
2023-10-10 13:46:07 +01:00
|
|
|
mp_machine_uart_init_helper(self, n_args - 1, args + 1, &kw_args);
|
2021-01-20 13:34:08 +00:00
|
|
|
|
|
|
|
return MP_OBJ_FROM_PTR(self);
|
|
|
|
}
|
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC void mp_machine_uart_deinit(machine_uart_obj_t *self) {
|
2022-01-20 18:45:31 +00:00
|
|
|
uart_deinit(self->uart);
|
|
|
|
if (self->uart_id == 0) {
|
|
|
|
irq_set_enabled(UART0_IRQ, false);
|
|
|
|
} else {
|
|
|
|
irq_set_enabled(UART1_IRQ, false);
|
|
|
|
}
|
|
|
|
self->baudrate = 0;
|
|
|
|
MP_STATE_PORT(rp2_uart_rx_buffer[self->uart_id]) = NULL;
|
|
|
|
MP_STATE_PORT(rp2_uart_tx_buffer[self->uart_id]) = NULL;
|
|
|
|
}
|
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC mp_int_t mp_machine_uart_any(machine_uart_obj_t *self) {
|
2021-03-11 07:36:16 +00:00
|
|
|
// get all bytes from the fifo first
|
|
|
|
uart_drain_rx_fifo(self);
|
2023-10-10 13:46:07 +01:00
|
|
|
return ringbuf_avail(&self->read_buffer);
|
2021-01-20 13:34:08 +00:00
|
|
|
}
|
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC bool mp_machine_uart_txdone(machine_uart_obj_t *self) {
|
|
|
|
return ringbuf_avail(&self->write_buffer) == 0
|
|
|
|
&& (uart_get_hw(self->uart)->fr & UART_UARTFR_TXFE_BITS);
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC void mp_machine_uart_sendbreak(machine_uart_obj_t *self) {
|
2021-01-20 13:34:08 +00:00
|
|
|
uart_set_break(self->uart, true);
|
|
|
|
mp_hal_delay_us(13000000 / self->baudrate + 1);
|
|
|
|
uart_set_break(self->uart, false);
|
2022-08-26 11:47:34 +01:00
|
|
|
}
|
2021-02-10 13:07:18 +00:00
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC mp_uint_t mp_machine_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) {
|
2021-01-20 13:34:08 +00:00
|
|
|
machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2023-11-30 03:34:07 +00:00
|
|
|
mp_uint_t start = mp_hal_ticks_ms();
|
|
|
|
mp_uint_t timeout = self->timeout;
|
2021-01-20 13:34:08 +00:00
|
|
|
uint8_t *dest = buf_in;
|
2021-02-09 14:50:21 +00:00
|
|
|
|
|
|
|
for (size_t i = 0; i < size; i++) {
|
|
|
|
// Wait for the first/next character
|
2021-03-11 07:36:16 +00:00
|
|
|
while (ringbuf_avail(&self->read_buffer) == 0) {
|
2021-07-23 13:04:36 +01:00
|
|
|
if (uart_is_readable(self->uart)) {
|
|
|
|
// Force a few incoming bytes to the buffer
|
|
|
|
uart_drain_rx_fifo(self);
|
|
|
|
break;
|
|
|
|
}
|
2023-11-30 03:34:07 +00:00
|
|
|
mp_uint_t elapsed = mp_hal_ticks_ms() - start;
|
|
|
|
if (elapsed > timeout) { // timed out
|
2021-02-09 14:50:21 +00:00
|
|
|
if (i <= 0) {
|
|
|
|
*errcode = MP_EAGAIN;
|
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
} else {
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
}
|
2023-11-30 03:34:07 +00:00
|
|
|
mp_event_wait_ms(timeout - elapsed);
|
2021-01-20 13:34:08 +00:00
|
|
|
}
|
2021-03-11 07:36:16 +00:00
|
|
|
*dest++ = ringbuf_get(&(self->read_buffer));
|
2023-11-30 03:34:07 +00:00
|
|
|
start = mp_hal_ticks_ms(); // Inter-character timeout
|
|
|
|
timeout = self->timeout_char;
|
2021-01-20 13:34:08 +00:00
|
|
|
}
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC mp_uint_t mp_machine_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) {
|
2021-01-20 13:34:08 +00:00
|
|
|
machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2023-11-30 03:34:07 +00:00
|
|
|
mp_uint_t start = mp_hal_ticks_ms();
|
|
|
|
mp_uint_t timeout = self->timeout;
|
2021-01-20 13:34:08 +00:00
|
|
|
const uint8_t *src = buf_in;
|
2021-03-11 07:36:16 +00:00
|
|
|
size_t i = 0;
|
2021-02-09 14:50:21 +00:00
|
|
|
|
2021-03-11 07:36:16 +00:00
|
|
|
// Put as many bytes as possible into the transmit buffer.
|
|
|
|
while (i < size && ringbuf_free(&(self->write_buffer)) > 0) {
|
|
|
|
ringbuf_put(&(self->write_buffer), *src++);
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Kickstart the UART transmit.
|
|
|
|
uart_fill_tx_fifo(self);
|
|
|
|
|
|
|
|
// Send the next characters while busy waiting.
|
|
|
|
while (i < size) {
|
|
|
|
// Wait for the first/next character to be sent.
|
|
|
|
while (ringbuf_free(&(self->write_buffer)) == 0) {
|
2023-11-30 03:34:07 +00:00
|
|
|
mp_uint_t elapsed = mp_hal_ticks_ms() - start;
|
|
|
|
if (elapsed > timeout) { // timed out
|
2021-02-09 14:50:21 +00:00
|
|
|
if (i <= 0) {
|
|
|
|
*errcode = MP_EAGAIN;
|
|
|
|
return MP_STREAM_ERROR;
|
|
|
|
} else {
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
}
|
2023-11-30 03:34:07 +00:00
|
|
|
mp_event_wait_ms(timeout - elapsed);
|
2021-01-20 13:34:08 +00:00
|
|
|
}
|
2021-03-11 07:36:16 +00:00
|
|
|
ringbuf_put(&(self->write_buffer), *src++);
|
|
|
|
++i;
|
2023-11-30 03:34:07 +00:00
|
|
|
start = mp_hal_ticks_ms(); // Inter-character timeout
|
|
|
|
timeout = self->timeout_char;
|
2021-03-11 07:36:16 +00:00
|
|
|
uart_fill_tx_fifo(self);
|
2021-01-20 13:34:08 +00:00
|
|
|
}
|
2021-03-11 07:36:16 +00:00
|
|
|
|
|
|
|
// Just in case the fifo was drained during refill of the ringbuf.
|
2021-01-20 13:34:08 +00:00
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2023-10-10 13:46:07 +01:00
|
|
|
STATIC mp_uint_t mp_machine_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) {
|
2021-01-20 13:34:08 +00:00
|
|
|
machine_uart_obj_t *self = self_in;
|
|
|
|
mp_uint_t ret;
|
|
|
|
if (request == MP_STREAM_POLL) {
|
|
|
|
uintptr_t flags = arg;
|
|
|
|
ret = 0;
|
2021-07-19 22:58:26 +01:00
|
|
|
if ((flags & MP_STREAM_POLL_RD) && (uart_is_readable(self->uart) || ringbuf_avail(&self->read_buffer) > 0)) {
|
2021-01-20 13:34:08 +00:00
|
|
|
ret |= MP_STREAM_POLL_RD;
|
|
|
|
}
|
2021-03-11 07:36:16 +00:00
|
|
|
if ((flags & MP_STREAM_POLL_WR) && ringbuf_free(&self->write_buffer) > 0) {
|
2021-01-20 13:34:08 +00:00
|
|
|
ret |= MP_STREAM_POLL_WR;
|
|
|
|
}
|
2022-08-26 11:47:34 +01:00
|
|
|
} else if (request == MP_STREAM_FLUSH) {
|
|
|
|
// The timeout is estimated using the buffer size and the baudrate.
|
|
|
|
// Take the worst case assumptions at 13 bit symbol size times 2.
|
|
|
|
uint64_t timeout = time_us_64() +
|
|
|
|
(uint64_t)(33 + self->write_buffer.size) * 13000000ll * 2 / self->baudrate;
|
2023-11-30 03:34:07 +00:00
|
|
|
while (1) {
|
2023-10-10 13:46:07 +01:00
|
|
|
if (mp_machine_uart_txdone(self)) {
|
2022-08-26 11:47:34 +01:00
|
|
|
return 0;
|
|
|
|
}
|
2023-11-30 03:34:07 +00:00
|
|
|
uint64_t now = time_us_64();
|
|
|
|
if (now >= timeout) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
mp_event_wait_ms((timeout - now) / 1000);
|
|
|
|
}
|
2022-08-26 11:47:34 +01:00
|
|
|
*errcode = MP_ETIMEDOUT;
|
|
|
|
ret = MP_STREAM_ERROR;
|
2021-01-20 13:34:08 +00:00
|
|
|
} else {
|
|
|
|
*errcode = MP_EINVAL;
|
|
|
|
ret = MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-07-01 20:47:42 +01:00
|
|
|
MP_REGISTER_ROOT_POINTER(void *rp2_uart_rx_buffer[2]);
|
|
|
|
MP_REGISTER_ROOT_POINTER(void *rp2_uart_tx_buffer[2]);
|