cc3200: Fix UART tests after correcting uart.read() behaviour.

This commit is contained in:
danicampora 2015-10-21 14:54:16 +02:00
parent be2879ce89
commit 075ca64521
2 changed files with 11 additions and 12 deletions

View File

@ -65,7 +65,7 @@
*******-***********************************************************************/
#define PYBUART_FRAME_TIME_US(baud) ((11 * 1000000) / baud)
#define PYBUART_2_FRAMES_TIME_US(baud) (PYBUART_FRAME_TIME_US(baud) * 2)
#define PYBUART_RX_TIMEOUT_US(baud) (PYBUART_2_FRAMES_TIME_US(baud))
#define PYBUART_RX_TIMEOUT_US(baud) (PYBUART_2_FRAMES_TIME_US(baud) * 8) // we need at least characters in the FIFO
#define PYBUART_TX_WAIT_US(baud) ((PYBUART_FRAME_TIME_US(baud)) + 1)
#define PYBUART_TX_MAX_TIMEOUT_MS (5)

View File

@ -54,7 +54,7 @@ print(uart1.read() == b'123456')
print(uart1.write(b'123') == 3)
print(uart0.read(1) == b'1')
print(uart0.read(2) == b'23')
print(uart0.read() == b'')
print(uart0.read() == None)
uart0.write(b'123')
buf = bytearray(3)
@ -79,28 +79,28 @@ uart0 = UART(0, 1000000, pins=('GP12', None))
print(uart0.write(b'123456') == 6)
print(uart1.read() == b'123456')
print(uart1.write(b'123') == 3)
print(uart0.read() == b'')
print(uart0.read() == None)
# rx only mode
uart0 = UART(0, 1000000, pins=(None, 'GP13'))
print(uart0.write(b'123456') == 6)
print(uart1.read() == b'')
print(uart1.read() == None)
print(uart1.write(b'123') == 3)
print(uart0.read() == b'123')
# leave pins as they were (rx only mode)
uart0 = UART(0, 1000000, pins=None)
print(uart0.write(b'123456') == 6)
print(uart1.read() == b'')
print(uart1.read() == None)
print(uart1.write(b'123') == 3)
print(uart0.read() == b'123')
# no pin assignemnt
uart0 = UART(0, 1000000, pins=(None, None))
print(uart0.write(b'123456789') == 9)
print(uart1.read() == b'')
print(uart1.read() == None)
print(uart1.write(b'123456789') == 9)
print(uart0.read() == b'')
print(uart0.read() == None)
print(Pin.board.GP12)
print(Pin.board.GP13)
@ -156,4 +156,3 @@ for uart_id in uart_id_range:
uart.init(115200)
print(uart)
uart.read()