stmhal: Fix linker map for STM32L476 chips.
In particular, this makes the L4 .isr_vector section 16K in size so it's the same as the F4/F7 MCUs. The patch also moves the L4 filesystem to the end of flash, which allows for 512K filesystem on the 1Mb devices like the STM32L476DISC.
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@ -313,11 +313,13 @@ else
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$(Q)$(DFU_UTIL) -a 0 -d $(DEVICE) -D $<
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$(Q)$(DFU_UTIL) -a 0 -d $(DEVICE) -D $<
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endif
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endif
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TEXT_ADDR ?= 0x08020000
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deploy-stlink: $(BUILD)/firmware.dfu
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deploy-stlink: $(BUILD)/firmware.dfu
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$(ECHO) "Writing $(BUILD)/firmware0.bin to the board via ST-LINK"
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$(ECHO) "Writing $(BUILD)/firmware0.bin to the board via ST-LINK"
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$(Q)$(STFLASH) write $(BUILD)/firmware0.bin 0x08000000
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$(Q)$(STFLASH) write $(BUILD)/firmware0.bin 0x08000000
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$(ECHO) "Writing $(BUILD)/firmware1.bin to the board via ST-LINK"
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$(ECHO) "Writing $(BUILD)/firmware1.bin to the board via ST-LINK"
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$(Q)$(STFLASH) --reset write $(BUILD)/firmware1.bin 0x08020000
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$(Q)$(STFLASH) --reset write $(BUILD)/firmware1.bin $(TEXT_ADDR)
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deploy-openocd: $(BUILD)/firmware.dfu
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deploy-openocd: $(BUILD)/firmware.dfu
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$(ECHO) "Writing $(BUILD)/firmware{0,1}.bin to the board via ST-LINK using OpenOCD"
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$(ECHO) "Writing $(BUILD)/firmware{0,1}.bin to the board via ST-LINK using OpenOCD"
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@ -327,7 +329,7 @@ $(BUILD)/firmware.dfu: $(BUILD)/firmware.elf
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$(ECHO) "Create $@"
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$(ECHO) "Create $@"
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$(Q)$(OBJCOPY) -O binary -j .isr_vector $^ $(BUILD)/firmware0.bin
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$(Q)$(OBJCOPY) -O binary -j .isr_vector $^ $(BUILD)/firmware0.bin
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$(Q)$(OBJCOPY) -O binary -j .text -j .data $^ $(BUILD)/firmware1.bin
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$(Q)$(OBJCOPY) -O binary -j .text -j .data $^ $(BUILD)/firmware1.bin
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$(Q)$(PYTHON) $(DFU) -b 0x08000000:$(BUILD)/firmware0.bin -b 0x08020000:$(BUILD)/firmware1.bin $@
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$(Q)$(PYTHON) $(DFU) -b 0x08000000:$(BUILD)/firmware0.bin -b $(TEXT_ADDR):$(BUILD)/firmware1.bin $@
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$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
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$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
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$(ECHO) "Create $@"
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$(ECHO) "Create $@"
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@ -2,3 +2,4 @@ MCU_SERIES = l4
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CMSIS_MCU = STM32L476xx
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CMSIS_MCU = STM32L476xx
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AF_FILE = boards/stm32l476_af.csv
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AF_FILE = boards/stm32l476_af.csv
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LD_FILE = boards/stm32l476xe.ld
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LD_FILE = boards/stm32l476xe.ld
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TEXT_ADDR = 0x08004000
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@ -2,3 +2,4 @@ MCU_SERIES = l4
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CMSIS_MCU = STM32L476xx
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CMSIS_MCU = STM32L476xx
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AF_FILE = boards/stm32l476_af.csv
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AF_FILE = boards/stm32l476_af.csv
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LD_FILE = boards/stm32l476xg.ld
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LD_FILE = boards/stm32l476xg.ld
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TEXT_ADDR = 0x08004000
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@ -6,9 +6,9 @@
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MEMORY
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MEMORY
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{
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
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FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x0000800 /* sector 0, 2 KiB */
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FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x0004000 /* sectors 0-7, 16 KiB */
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FLASH_FS (r) : ORIGIN = 0x08000800, LENGTH = 0x001F800 /* sectors 1-63 (2K each = 126 KiB) */
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FLASH_TEXT (rx) : ORIGIN = 0x08004000, LENGTH = 0x005C000 /* sectors 8-191, 368 KiB */
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FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x0060000 /* Sector starting @ 64 */
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FLASH_FS (r) : ORIGIN = 0x08060000, LENGTH = 0x0020000 /* sectors 192-255, 128 KiB */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
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SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K
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SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K
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}
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}
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@ -30,3 +30,6 @@ _ram_start = ORIGIN(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_heap_start = _ebss; /* heap starts just after statically allocated memory */
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_heap_start = _ebss; /* heap starts just after statically allocated memory */
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_heap_end = 0x20014000; /* tunable */
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_heap_end = 0x20014000; /* tunable */
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_flash_fs_start = ORIGIN(FLASH_FS);
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_flash_fs_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
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@ -6,9 +6,9 @@
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MEMORY
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MEMORY
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{
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x0000800 /* sector 0, 2 KiB */
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FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 0x0004000 /* sectors 0-7, 16 KiB */
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FLASH_FS (r) : ORIGIN = 0x08000800, LENGTH = 0x001F800 /* sectors 1-63 (2K each = 126 KiB) */
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FLASH_TEXT (rx) : ORIGIN = 0x08004000, LENGTH = 0x007C000 /* sectors 8-255, 496 KiB */
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FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 0x0080000 /* Sector starting @ 64 */
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FLASH_FS (r) : ORIGIN = 0x08080000, LENGTH = 0x0080000 /* sectors 256-511 512 KiB */
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
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SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K
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SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K
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}
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}
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@ -32,3 +32,6 @@ _ram_start = ORIGIN(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_ram_end = ORIGIN(RAM) + LENGTH(RAM);
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_heap_start = _ebss; /* heap starts just after statically allocated memory */
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_heap_start = _ebss; /* heap starts just after statically allocated memory */
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_heap_end = 0x20014000; /* tunable */
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_heap_end = 0x20014000; /* tunable */
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_flash_fs_start = ORIGIN(FLASH_FS);
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_flash_fs_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
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@ -86,11 +86,14 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
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#elif defined(STM32L476xx)
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#elif defined(STM32L476xx)
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extern uint8_t _flash_fs_start;
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extern uint8_t _flash_fs_end;
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// The STM32L476 doesn't have CCRAM, so we use the 32K SRAM2 for this.
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// The STM32L476 doesn't have CCRAM, so we use the 32K SRAM2 for this.
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#define CACHE_MEM_START_ADDR (0x10000000) // SRAM2 data RAM, 32k
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#define CACHE_MEM_START_ADDR (0x10000000) // SRAM2 data RAM, 32k
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#define FLASH_SECTOR_SIZE_MAX (0x00800) // 2k max
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#define FLASH_SECTOR_SIZE_MAX (0x00800) // 2k max
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#define FLASH_MEM_SEG1_START_ADDR (0x08000800) // sector 1
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#define FLASH_MEM_SEG1_START_ADDR ((long)&_flash_fs_start)
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#define FLASH_MEM_SEG1_NUM_BLOCKS (252) // 1 Block=512 Bytes Reserve 126 kBytes
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#define FLASH_MEM_SEG1_NUM_BLOCKS ((&_flash_fs_end - &_flash_fs_start) / 512)
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#else
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#else
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#error "no storage support for this MCU"
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#error "no storage support for this MCU"
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