stm32/machine_i2s: Improve accuracy of SCK frequency.
Configures the I2S PLL to produce a frequency that the I2S clock generator can use to create an optimal SCK frequency. The I2S PLL configuration table is automatically generated at build time. Fixes issue #10280. Signed-off-by: Mike Teachman <mike.teachman@gmail.com>
This commit is contained in:
MikeTeachman
Damien George
parent
f3889db265
commit
58112fc49a
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@ -65,6 +65,7 @@ OPENOCD_CONFIG ?= boards/openocd_stm32f4.cfg
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include stm32.mk
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PLLVALUES = boards/pllvalues.py
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PLLI2SVALUES = boards/plli2svalues.py
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MAKE_PINS = boards/make-pins.py
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BOARD_PINS = $(BOARD_DIR)/pins.csv
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PREFIX_FILE = boards/stm32f4xx_prefix.c
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@ -82,6 +83,7 @@ GEN_CDCINF_FILE = $(HEADER_BUILD)/pybcdc.inf
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GEN_CDCINF_HEADER = $(HEADER_BUILD)/pybcdc_inf.h
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GEN_PLLFREQTABLE_HDR = $(HEADER_BUILD)/pllfreqtable.h
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GEN_PLLI2STABLE_HDR = $(HEADER_BUILD)/plli2stable.h
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GEN_STMCONST_HDR = $(HEADER_BUILD)/modstm_const.h
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GEN_STMCONST_MPZ = $(HEADER_BUILD)/modstm_mpz.h
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CMSIS_MCU_HDR = $(STM32LIB_CMSIS_ABS)/Include/$(CMSIS_MCU_LOWER).h
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@ -681,6 +683,11 @@ $(GEN_PLLFREQTABLE_HDR): $(PLLVALUES) | $(HEADER_BUILD)
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$(ECHO) "GEN $@"
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$(Q)$(PYTHON) $(PLLVALUES) -c -m $(CMSIS_MCU_LOWER) file:$(BOARD_DIR)/stm32$(MCU_SERIES)xx_hal_conf.h > $@
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$(TOP)/extmod/machine_i2s.c: $(GEN_PLLI2STABLE_HDR)
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$(GEN_PLLI2STABLE_HDR): $(PLLI2SVALUES) | $(HEADER_BUILD)
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$(ECHO) "GEN $@"
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$(Q)$(PYTHON) $(PLLI2SVALUES) -c -m $(CMSIS_MCU_LOWER) hse:$(BOARD_DIR)/stm32$(MCU_SERIES)xx_hal_conf.h pllm:$(BOARD_DIR)/mpconfigboard.h > $@
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$(BUILD)/modstm.o: $(GEN_STMCONST_HDR)
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$(HEADER_BUILD)/modstm_const.h: $(CMSIS_MCU_HDR) make-stmconst.py | $(HEADER_BUILD)
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$(ECHO) "GEN stmconst $@"
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@ -0,0 +1,213 @@
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"""
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This program computes I2S PLL parameters for STM32
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processors supporting an I2S PLL in the clock tree.
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Those processors are listed below in the mcu_support_plli2s[] list.
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"""
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import re
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from collections import namedtuple
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class MCU:
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def __init__(self, range_plli2sn, range_plli2sr):
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self.range_plli2sn = range_plli2sn
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self.range_plli2sr = range_plli2sr
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mcu_default = MCU(range_plli2sn=range(50, 432 + 1), range_plli2sr=range(2, 7 + 1))
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mcu_table = {"stm32f401xe": MCU(range_plli2sn=range(192, 432 + 1), range_plli2sr=range(2, 7 + 1))}
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# list of stm32 processors that support an I2S PLL in the clock tree
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mcu_support_plli2s = [
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"stm32f405xx",
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"stm32f401xe",
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"stm32f407xx",
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"stm32f411xe",
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"stm32f412zx",
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"stm32f413xx",
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"stm32f427xx",
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"stm32f429xx",
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"stm32f439xx",
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"stm32f446xx",
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"stm32f722xx",
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"stm32f733xx",
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"stm32f746xx",
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"stm32f756xx",
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"stm32f767xx",
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"stm32f769xx",
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]
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# The following function calculates the multiplier (plli2sn) and divider (plli2sr) parameters
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# for the I2S PLL that leads to the best possible accuracy for the I2S sampling clock.
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# This is done by creating a set of candidate parameters (plli2sn, plli2sr)
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# and then determining which candidate parameters lead to a sampling clock frequency (Fs)
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# that most closely matches the desired sampling clock frequency (I2S rate).
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#
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# A description of the clock tree helps to understand this function:
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# The clock tree on a STM32 device is complex. A subset of the clock tree is used for I2S, as follows:
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# 1. HSE clock is divided by the PLLM divider and feeds the I2S PLL (called PLLI2S in the STM32 clock tree).
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# 2. The output frequency of the I2S PLL is controlled by two parameters, plli2sn and plli2sr.
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# 3. The clock output of the I2S PLL is called PLLI2SCLK
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# 4. PLLI2SCLK is gated into the I2S peripheral, where the name changes to I2SxCLK
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# 5. I2SxCLK is an input to the I2S clock generator.
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# 6. The output frequency of the I2S clock generator is controlled by
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# two configuration parameters, I2SDIV and ODD.
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# 7. The output of the I2S clock generator is the audio sampling frequency (Fs),
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# which is used to create the signal at the I2S WS output pin.
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#
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# Example references:
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# RM0090 Reference manual STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439
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# - section 6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
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# - section 28.4.4 Clock generator
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# RM0385 Reference manual STM32F75xxx and STM32F74xxx
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# - section 5.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
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# - section 32.7.5 Clock generator
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#
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# The calculations below mimic the fixed-point integer calculations in the STM32 I2S driver,
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# in the function HAL_I2S_Init().
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def compute_plli2s_table(hse, pllm):
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plli2s = namedtuple("plli2s", "bits rate plli2sn plli2sr i2sdiv odd error")
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plli2s_table = []
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for bits in (16, 32):
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for rate in (8_000, 11_025, 12_000, 16_000, 22_050, 24_000, 32_000, 44_100, 48_000):
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plli2s_candidates = []
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for plli2sn in mcu.range_plli2sn:
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for plli2sr in mcu.range_plli2sr:
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I2SxCLK = hse // pllm * plli2sn // plli2sr
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if I2SxCLK < 192_000_000:
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# compute I2S clock generator parameters: i2sdiv, odd
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tmp = (((I2SxCLK // (bits * 2)) * 10) // rate) + 5
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tmp = tmp // 10
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odd = tmp & 1
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i2sdiv = (tmp - odd) // 2
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Fs = I2SxCLK / ((bits * 2) * ((2 * i2sdiv) + odd))
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error = (abs(Fs - rate) / rate) * 100
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plli2s_candidates.append(
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plli2s(
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bits=bits,
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rate=rate,
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plli2sn=plli2sn,
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plli2sr=plli2sr,
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i2sdiv=i2sdiv,
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odd=odd,
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error=error,
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)
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)
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# sort based on error
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plli2s_candidates_sorted = sorted(plli2s_candidates, key=lambda x: x.error)
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# select the best candidate
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plli2s_table.append(plli2s_candidates_sorted[0])
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return plli2s_table
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def generate_c_table(plli2s_table, hse, pllm):
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print("// MAKE generated file, created by plli2svalues.py: DO NOT EDIT")
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print("// This table is used in machine_i2s.c")
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print(f"// HSE_VALUE = {hse}")
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print(f"// MICROPY_HW_CLK_PLLM = {pllm} \n")
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print("#define PLLI2S_TABLE \\")
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print("{ \\")
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for plli2s in plli2s_table:
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print(
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f" {{{plli2s.rate}, "
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f"{plli2s.bits}, "
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f"{plli2s.plli2sr}, "
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f"{plli2s.plli2sn} }}, "
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f"/* i2sdiv: {int(plli2s.i2sdiv)}, "
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f"odd: {plli2s.odd}, "
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f"rate error % (desired vs actual)%: {plli2s.error:.4f} */ \\"
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)
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print("}")
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def search_header(filename, re_include, re_define, lookup, val):
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regex_include = re.compile(re_include)
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regex_define = re.compile(re_define)
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with open(filename) as f:
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for line in f:
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line = line.strip()
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m = regex_include.match(line)
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if m:
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# Search included file
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search_header(m.group(1), re_include, re_define, lookup, val)
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continue
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m = regex_define.match(line)
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if m:
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# found lookup value
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if m.group(1) == lookup:
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val[0] = int(m.group(3))
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return val
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def main():
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global mcu
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# parse input args
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import sys
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argv = sys.argv[1:]
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c_table = False
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mcu_series = "stm32f4"
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hse = None
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pllm = None
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while True:
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if argv[0] == "-c":
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c_table = True
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argv.pop(0)
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elif argv[0] == "-m":
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argv.pop(0)
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mcu_series = argv.pop(0).lower()
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else:
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break
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if mcu_series in mcu_support_plli2s:
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if len(argv) != 2:
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print("usage: pllvalues.py [-c] [-m <mcu_series>] <hse in MHz> <pllm in MHz>")
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sys.exit(1)
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if argv[0].startswith("hse:"):
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# extract HSE_VALUE from header file
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(hse,) = search_header(
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argv[0][len("hse:") :],
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r'#include "(boards/[A-Za-z0-9_./]+)"',
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r"#define +(HSE_VALUE) +\((\(uint32_t\))?([0-9]+)\)",
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"HSE_VALUE",
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[None],
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)
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if hse is None:
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raise ValueError("%s does not contain a definition of HSE_VALUE" % argv[0])
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argv.pop(0)
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if argv[0].startswith("pllm:"):
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# extract MICROPY_HW_CLK_PLLM from header file
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(pllm,) = search_header(
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argv[0][len("pllm:") :],
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r'#include "(boards/[A-Za-z0-9_./]+)"',
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r"#define +(MICROPY_HW_CLK_PLLM) +\((\(uint32_t\))?([0-9]+)\)",
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"MICROPY_HW_CLK_PLLM",
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[None],
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)
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if pllm is None:
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raise ValueError(
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"%s does not contain a definition of MICROPY_HW_CLK_PLLM" % argv[0]
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)
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argv.pop(0)
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# Select MCU parameters
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mcu = mcu_default
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for m in mcu_table:
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if mcu_series.startswith(m):
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mcu = mcu_table[m]
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break
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plli2s_table = compute_plli2s_table(hse, pllm)
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if c_table:
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generate_c_table(plli2s_table, hse, pllm)
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if __name__ == "__main__":
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main()
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@ -33,6 +33,7 @@
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#include "py/mphal.h"
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#include "pin.h"
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#include "dma.h"
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#include "genhdr/plli2stable.h"
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// Notes on this port's specific implementation of I2S:
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// - the DMA callbacks (1/2 complete and complete) are used to implement the asynchronous background operations
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@ -61,6 +62,13 @@ typedef enum {
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BOTTOM_HALF
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} ping_pong_t;
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typedef struct _plli2s_config_t {
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uint32_t rate;
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uint8_t bits;
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uint8_t plli2sr;
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uint16_t plli2sn;
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} plli2s_config_t;
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typedef struct _machine_i2s_obj_t {
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mp_obj_base_t base;
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uint8_t i2s_id;
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@ -98,12 +106,26 @@ STATIC const int8_t i2s_frame_map[NUM_I2S_USER_FORMATS][I2S_RX_FRAME_SIZE_IN_BYT
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{ 2, 3, 0, 1, 6, 7, 4, 5 }, // Stereo, 32-bits
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};
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STATIC const plli2s_config_t plli2s_config[] = PLLI2S_TABLE;
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void machine_i2s_init0() {
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for (uint8_t i = 0; i < MICROPY_HW_MAX_I2S; i++) {
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MP_STATE_PORT(machine_i2s_obj)[i] = NULL;
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}
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}
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STATIC bool lookup_plli2s_config(int8_t bits, int32_t rate, uint16_t *plli2sn, uint16_t *plli2sr) {
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for (uint16_t i = 0; i < MP_ARRAY_SIZE(plli2s_config); i++) {
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if ((plli2s_config[i].bits == bits) && (plli2s_config[i].rate == rate)) {
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*plli2sn = plli2s_config[i].plli2sn;
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*plli2sr = plli2s_config[i].plli2sr;
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return true;
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}
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}
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return false;
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}
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// For 32-bit audio samples, the STM32 HAL API expects each 32-bit sample to be encoded
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// in an unusual byte ordering: Byte_2, Byte_3, Byte_0, Byte_1
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// where: Byte_0 is the least significant byte of the 32-bit sample
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@ -294,6 +316,29 @@ STATIC bool i2s_init(machine_i2s_obj_t *self) {
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HAL_GPIO_Init(self->sd->gpio, &GPIO_InitStructure);
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}
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// configure I2S PLL
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S;
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// lookup optimal PLL multiplier (PLLI2SN) and divisor (PLLI2SR) for a given sample size and sampling frequency
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uint16_t plli2sn;
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uint16_t plli2sr;
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if (lookup_plli2s_config(self->mode == I2S_MODE_MASTER_RX ? 32 : self->bits, self->rate, &plli2sn, &plli2sr)) {
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// match found
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PeriphClkInitStruct.PLLI2S.PLLI2SN = plli2sn;
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PeriphClkInitStruct.PLLI2S.PLLI2SR = plli2sr;
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} else {
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// no match for sample size and rate
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// configure PLL to use power-on default values when a non-standard sampling frequency is used
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PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
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PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
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}
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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return false;
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}
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if (HAL_I2S_Init(&self->hi2s) == HAL_OK) {
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// Reset and initialize Tx and Rx DMA channels
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if (self->mode == I2S_MODE_MASTER_RX) {
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@ -306,13 +351,10 @@ STATIC bool i2s_init(machine_i2s_obj_t *self) {
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self->hi2s.hdmatx = &self->hdma_tx;
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}
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__HAL_RCC_PLLI2S_ENABLE(); // start I2S clock
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return true;
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} else {
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return false;
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}
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}
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void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) {
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