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docs/machine.SPI.rst: Fix typos and formatting, clarify. 

Clarify the class implements master side of the protocol, also put adhoc
WiPy paramter after the generic, described in the current Hardware API
version.
This commit is contained in:
Paul Sokolovsky 2016-10-25 17:03:35 +03:00
parent 760ed4629f
commit 67c91df7e8
1 changed files with 12 additions and 10 deletions
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22
docs/library/machine.SPI.rst
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@ -1,13 +1,14 @@
.. currentmodule:: machine .. currentmodule:: machine
class SPI -- a Serial Peripheral Interface bus protocol class SPI -- a Serial Peripheral Interface bus protocol (master side)
======================================================= =====================================================================
SPI is a serial protocol that is driven by a master. At the physical level, SPI is a synchronous serial protocol that is driven by a master. At the
bus consistens of 3 lines: SCK, MOSI, MISO. Multiple devices can share the physical level, a bus consists of 3 lines: SCK, MOSI, MISO. Multiple devices
same bus. Each device should have a separate, 4th signal, SS (Slave Select), can share the same bus. Each device should have a separate, 4th signal,
to select a particualr device on a bus with which communication takes place. SS (Slave Select), to select a particualr device on a bus with which
Management of an SS signal should happen in user code (via machine.Pin class). communication takes place. Management of an SS signal should happen in
user code (via machine.Pin class).
.. only:: port_wipy .. only:: port_wipy
@ -39,7 +40,7 @@ Constructors
Methods Methods
------- -------
.. method:: SPI.init(baudrate=1000000, \*, polarity=0, phase=0, bits=8, firstbit=SPI.MSB, pins=(CLK, MOSI, MISO), sck=None, mosi=None, miso=None) .. method:: SPI.init(baudrate=1000000, \*, polarity=0, phase=0, bits=8, firstbit=SPI.MSB, sck=None, mosi=None, miso=None, pins=(SCK, MOSI, MISO))
Initialise the SPI bus with the given parameters: Initialise the SPI bus with the given parameters:
@ -49,12 +50,13 @@ Methods
respectively. respectively.
- ``bits`` is the width in bits of each transfer. Only 8 is guaranteed to be supported by all hardware. - ``bits`` is the width in bits of each transfer. Only 8 is guaranteed to be supported by all hardware.
- ``firstbit`` can be ``SPI.MSB`` or ``SPI.LSB``. - ``firstbit`` can be ``SPI.MSB`` or ``SPI.LSB``.
- ``pins`` is an optional tuple with the pins to assign to the SPI bus (deprecated, only for WiPy).
- ``sck``, ``mosi``, ``miso`` are pins (machine.Pin) objects to use for bus signals. For most - ``sck``, ``mosi``, ``miso`` are pins (machine.Pin) objects to use for bus signals. For most
hardware SPI blocks (as selected by ``id`` parameter to the constructore), pins are fixed hardware SPI blocks (as selected by ``id`` parameter to the constructore), pins are fixed
and cannot be changed. In some cases, hardware blocks allow 2-3 alternative pin sets for and cannot be changed. In some cases, hardware blocks allow 2-3 alternative pin sets for
a hardware SPI block. Arbitrary pin assignments are possible only for a bitbanging SPI driver a hardware SPI block. Arbitrary pin assignments are possible only for a bitbanging SPI driver
(``id``=-1). (``id`` = -1).
- ``pins`` - WiPy port doesn't ``sck``, ``mosi``, ``miso`` arguments, and instead allows to
specify them as a tuple of ``pins`` paramter.
.. method:: SPI.deinit() .. method:: SPI.deinit()