stm32/machine_adc: Fix and improve STM32H5 support.
Changes are: - Run ADC on PCLK/16. - Verify and optimize timings (ADC_STAB_DELAY_US, ADC_SAMPLETIME_DEFAULT). - Add support for STM32H5 VBAT and COREVDD channels on ADC2. - Replace ADC constants in machine_adc_locals_dict_table. - Convert STM32 literal to channel numbers in adc_config_channel with corresponding STM32 LL library functions (__LL_ADC_IS_CHANNEL_INTERNAL(), __LL_ADC_CHANNEL_TO_DECIMAL_NB()). Reasoning for the second last point: the STM32 driver literals are uint32_t that don't work with MP_ROM_INT() which handles signed 31 bit integers only. Introduce enumerator machine_adc_internal_ch_t to define external channels (0..19), internal channels (256..) and the special channel VREF (0xffff). Values are converted to STM32 literals with adc_ll_channel() when required in adc_config_and_read_u16(). Signed-off-by: Rene Straub <rene@see5.ch>
This commit is contained in:
Rene Straub
Damien George
parent
64d24fccd6
commit
72ef2e6291
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@ -48,7 +48,9 @@
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#elif defined(STM32G4)
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#define ADC_STAB_DELAY_US (20)
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#elif defined(STM32H5)
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#define ADC_STAB_DELAY_US (1) // TODO: Check if this is enough
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// Stabilization delay = 1 conversion cycle
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// ADC clk = PDIV / 16 = 250 MHz / 16 = 15.625 MHz -> 64 ns -> select 1 us
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#define ADC_STAB_DELAY_US (1)
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#elif defined(STM32L4)
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#define ADC_STAB_DELAY_US (10)
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#elif defined(STM32WB)
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@ -61,9 +63,14 @@
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#elif defined(STM32F4) || defined(STM32F7)
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#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_15CYCLES
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#define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_480CYCLES
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#elif defined(STM32G4) || defined(STM32H5)
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#elif defined(STM32G4)
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#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_12CYCLES_5
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#define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_247CYCLES_5
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#elif defined(STM32H5)
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// Worst case sampling time: slow channel, 12 bits, 680 ohms -> 165 ns
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// ADC clk = PDIV / 16 = 250 MHz / 16 = 15.625 MHz -> 64 ns -> 2.57 cycles -> select 6.5 cycles
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#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_6CYCLES_5
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#define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_247CYCLES_5
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#elif defined(STM32H7)
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#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_8CYCLES_5
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#define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_387CYCLES_5
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@ -81,8 +88,65 @@
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// Timeout for waiting for end-of-conversion
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#define ADC_EOC_TIMEOUT_MS (10)
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// This is a synthesised channel representing the maximum ADC reading (useful to scale other channels)
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#define ADC_CHANNEL_VREF (0xffff)
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// Channel IDs for machine.ADC object
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typedef enum _machine_adc_internal_ch_t {
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// Regular external ADC inputs (0..19)
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MACHINE_ADC_EXT_CH_0 = 0,
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MACHINE_ADC_EXT_CH_19 = 19,
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// Internal ADC channels (256..)
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MACHINE_ADC_INT_CH_VREFINT = 256,
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MACHINE_ADC_INT_CH_TEMPSENSOR,
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#if defined(ADC_CHANNEL_VBAT)
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MACHINE_ADC_INT_CH_VBAT,
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#endif
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#if defined(ADC_CHANNEL_VDDCORE)
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MACHINE_ADC_INT_CH_VDDCORE,
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#endif
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// This is a synthesised channel representing the maximum ADC reading (useful to scale other channels)
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MACHINE_ADC_CH_VREF = 0xffff // 0xffff for backward compatibility
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} machine_adc_internal_ch_t;
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// Convert machine_adc_internal_ch_t value to STM32 library ADC channel literal.
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// This function is required as literals are uint32_t types that don't map with MP_ROM_INT (31 bit signed).
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STATIC uint32_t adc_ll_channel(uint32_t channel_id) {
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uint32_t adc_ll_ch;
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switch (channel_id) {
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// external channels map 1:1
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case MACHINE_ADC_EXT_CH_0 ... MACHINE_ADC_EXT_CH_19:
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adc_ll_ch = channel_id;
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break;
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// internal channels are converted to STM32 ADC defines
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case MACHINE_ADC_INT_CH_VREFINT:
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adc_ll_ch = ADC_CHANNEL_VREFINT;
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break;
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case MACHINE_ADC_INT_CH_TEMPSENSOR:
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#if defined(STM32G4)
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adc_ll_ch = ADC_CHANNEL_TEMPSENSOR_ADC1;
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#else
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adc_ll_ch = ADC_CHANNEL_TEMPSENSOR;
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#endif
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break;
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#if defined(ADC_CHANNEL_VBAT)
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case MACHINE_ADC_INT_CH_VBAT:
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adc_ll_ch = ADC_CHANNEL_VBAT;
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break;
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#endif
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#if defined(ADC_CHANNEL_VDDCORE)
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case MACHINE_ADC_INT_CH_VDDCORE:
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adc_ll_ch = ADC_CHANNEL_VDDCORE;
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break;
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#endif
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// To save code memory for costly error handling, default to Vref for unknown channels
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default:
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adc_ll_ch = ADC_CHANNEL_VREFINT;
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break;
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};
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return adc_ll_ch;
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}
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static inline void adc_stabilisation_delay_us(uint32_t us) {
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mp_hal_delay_us(us + 1);
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@ -150,9 +214,9 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
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adc->CFGR2 = 2 << ADC_CFGR2_CKMODE_Pos; // PCLK/4 (synchronous clock mode)
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#elif defined(STM32F4) || defined(STM32F7) || defined(STM32L4)
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ADCx_COMMON->CCR = 0; // ADCPR=PCLK/2
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#elif defined(STM32G4)
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#elif defined(STM32G4) || defined(STM32H5)
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ADC12_COMMON->CCR = 7 << ADC_CCR_PRESC_Pos; // PCLK/16 (asynchronous clock mode)
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#elif defined(STM32H5) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
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#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
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ADC12_COMMON->CCR = 3 << ADC_CCR_CKMODE_Pos;
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#elif defined(STM32H7)
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ADC12_COMMON->CCR = 3 << ADC_CCR_CKMODE_Pos;
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@ -352,9 +416,16 @@ STATIC void adc_config_channel(ADC_TypeDef *adc, uint32_t channel, uint32_t samp
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#else
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adc_common->CCR |= ADC_CCR_VBATEN;
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#endif
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#if defined(STM32H5)
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} else if (channel == ADC_CHANNEL_VDDCORE) {
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adc->OR |= ADC_OR_OP0; // Enable Vddcore channel on ADC2
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#endif
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}
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#if defined(STM32G4) || defined(STM32H5)
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// G4 and H5 use encoded literals for internal channels -> extract ADC channel for following code
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if (__LL_ADC_IS_CHANNEL_INTERNAL(channel)) {
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channel = __LL_ADC_CHANNEL_TO_DECIMAL_NB(channel);
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}
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#if defined(STM32G4)
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channel = __LL_ADC_CHANNEL_TO_DECIMAL_NB(channel);
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adc->DIFSEL &= ~(1 << channel); // Set channel to Single-ended.
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#endif
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adc->SQR1 = (channel & 0x1f) << ADC_SQR1_SQ1_Pos | (1 - 1) << ADC_SQR1_L_Pos;
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@ -391,10 +462,13 @@ STATIC uint32_t adc_read_channel(ADC_TypeDef *adc) {
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}
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uint32_t adc_config_and_read_u16(ADC_TypeDef *adc, uint32_t channel, uint32_t sample_time) {
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if (channel == ADC_CHANNEL_VREF) {
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if (channel == MACHINE_ADC_CH_VREF) {
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return 0xffff;
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}
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// Map internal channel_id to STM32 ADC driver value/literal.
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channel = adc_ll_channel(channel);
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// Select, configure and read the channel.
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adc_config_channel(adc, channel, sample_time);
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uint32_t raw = adc_read_channel(adc);
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@ -421,7 +495,7 @@ const mp_obj_type_t machine_adc_type;
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typedef struct _machine_adc_obj_t {
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mp_obj_base_t base;
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ADC_TypeDef *adc;
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uint32_t channel;
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uint32_t channel; // one of machine_adc_internal_ch_t
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uint32_t sample_time;
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} machine_adc_obj_t;
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@ -452,20 +526,25 @@ STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, s
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uint32_t sample_time = ADC_SAMPLETIME_DEFAULT;
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ADC_TypeDef *adc;
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if (mp_obj_is_int(source)) {
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channel = mp_obj_get_int(source);
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#if defined(STM32WL)
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adc = ADC;
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#elif defined(STM32H5)
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// on STM32H5 vbat and vddcore channels are on ADC2
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if (channel == MACHINE_ADC_INT_CH_VBAT || channel == MACHINE_ADC_INT_CH_VDDCORE) {
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adc = ADC2;
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} else {
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adc = ADC1;
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}
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#else
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adc = ADC1;
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#endif
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channel = mp_obj_get_int(source);
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if (channel == ADC_CHANNEL_VREFINT
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#if defined(STM32G4)
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|| channel == ADC_CHANNEL_TEMPSENSOR_ADC1
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#else
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|| channel == ADC_CHANNEL_TEMPSENSOR
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#endif
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if (channel == MACHINE_ADC_INT_CH_VREFINT || channel == MACHINE_ADC_INT_CH_TEMPSENSOR
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#if defined(ADC_CHANNEL_VBAT)
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|| channel == ADC_CHANNEL_VBAT
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|| channel == MACHINE_ADC_INT_CH_VBAT
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#endif
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#if defined(ADC_CHANNEL_VDDCORE)
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|| channel == MACHINE_ADC_INT_CH_VDDCORE
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#endif
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) {
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sample_time = ADC_SAMPLETIME_DEFAULT_INT;
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@ -516,15 +595,14 @@ MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_read_u16_obj, machine_adc_read_u16);
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STATIC const mp_rom_map_elem_t machine_adc_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_read_u16), MP_ROM_PTR(&machine_adc_read_u16_obj) },
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{ MP_ROM_QSTR(MP_QSTR_VREF), MP_ROM_INT(ADC_CHANNEL_VREF) },
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{ MP_ROM_QSTR(MP_QSTR_CORE_VREF), MP_ROM_INT(ADC_CHANNEL_VREFINT) },
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#if defined(STM32G4)
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{ MP_ROM_QSTR(MP_QSTR_CORE_TEMP), MP_ROM_INT(ADC_CHANNEL_TEMPSENSOR_ADC1) },
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#else
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{ MP_ROM_QSTR(MP_QSTR_CORE_TEMP), MP_ROM_INT(ADC_CHANNEL_TEMPSENSOR) },
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#endif
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{ MP_ROM_QSTR(MP_QSTR_VREF), MP_ROM_INT(MACHINE_ADC_CH_VREF) },
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{ MP_ROM_QSTR(MP_QSTR_CORE_VREF), MP_ROM_INT(MACHINE_ADC_INT_CH_VREFINT) },
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{ MP_ROM_QSTR(MP_QSTR_CORE_TEMP), MP_ROM_INT(MACHINE_ADC_INT_CH_TEMPSENSOR) },
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#if defined(ADC_CHANNEL_VBAT)
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{ MP_ROM_QSTR(MP_QSTR_CORE_VBAT), MP_ROM_INT(ADC_CHANNEL_VBAT) },
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{ MP_ROM_QSTR(MP_QSTR_CORE_VBAT), MP_ROM_INT(MACHINE_ADC_INT_CH_VBAT) },
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#endif
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#if defined(ADC_CHANNEL_VDDCORE)
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{ MP_ROM_QSTR(MP_QSTR_CORE_VDD), MP_ROM_INT(MACHINE_ADC_INT_CH_VDDCORE) },
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#endif
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};
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STATIC MP_DEFINE_CONST_DICT(machine_adc_locals_dict, machine_adc_locals_dict_table);
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