renesas-ra/boards/VK_RA6M5: Add new board definition.
Signed-off-by: mbedNoobNinja <novoltage@gmail.com>
This commit is contained in:
mbedNoobNinja
Damien George
parent
fae96b17a7
commit
761d86ae56
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In case you need to debug something in `VK_RA6M5` board, make sure the contents of
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[project repo](https://github.com/Vekatech/VK_RA6M5) is cloned in to **this** directory.
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{
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"deploy": [
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"../deploy.md"
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],
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"docs": "",
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"features": [
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"UART",
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"SPI",
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"I2C",
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"ADC",
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"DAC",
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"PWM"
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],
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"id": "VK-RA6M5",
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"images": [
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"VK-RA6M5.jpg"
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],
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"mcu": "RA6M5",
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"product": "VK-RA6M5",
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"thumbnail": "",
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"url": "https://vekatech.com/VK-RA6M5_docs/brochures/VK-RA6M5%20Flyer%20R2.pdf",
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"vendor": "Vekatech"
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}
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// MCU config
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#define MICROPY_HW_BOARD_NAME "VK-RA6M5"
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#define MICROPY_HW_MCU_NAME "RA6M5"
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#define MICROPY_HW_MCU_SYSCLK 200000000
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#define MICROPY_HW_MCU_PCLK 100000000
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// module config
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#define MICROPY_EMIT_THUMB (1)
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#define MICROPY_EMIT_INLINE_THUMB (1)
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#define MICROPY_PY_BUILTINS_COMPLEX (1)
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#define MICROPY_PY_GENERATOR_PEND_THROW (1)
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#define MICROPY_PY_MATH (1)
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#define MICROPY_PY_UHEAPQ (1)
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#define MICROPY_PY_UTIMEQ (1)
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#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only
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// peripheral config
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#define MICROPY_HW_ENABLE_RTC (1)
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#define MICROPY_HW_RTC_SOURCE (1) // 0: subclock
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#define MICROPY_HW_ENABLE_ADC (1)
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#define MICROPY_HW_HAS_FLASH (1)
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#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
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#define MICROPY_HW_HAS_QSPI_FLASH (1)
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#define MICROPY_HW_HAS_SDHI_CARD (1)
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// board config
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// UART
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#define MICROPY_HW_UART7_TX (pin_P613) // D1
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#define MICROPY_HW_UART7_RX (pin_P614) // D0
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#define MICROPY_HW_UART6_TX (pin_P506) // Modbus (RS485)
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#define MICROPY_HW_UART6_RX (pin_P505) // Modbus (RS485)
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#define MICROPY_HW_UART9_TX (pin_P109) // REPL
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#define MICROPY_HW_UART9_RX (pin_P110) // REPL
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#define MICROPY_HW_UART_REPL HW_UART_9
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#define MICROPY_HW_UART_REPL_BAUD 115200
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// I2C
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#define MICROPY_HW_I2C2_SCL (pin_P415)
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#define MICROPY_HW_I2C2_SDA (pin_P414)
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// SPI
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#define MICROPY_HW_SPI0_SSL (pin_P301) // D10
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#define MICROPY_HW_SPI0_RSPCK (pin_P204) // D13
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#define MICROPY_HW_SPI0_MISO (pin_P202) // D12
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#define MICROPY_HW_SPI0_MOSI (pin_P203) // D11
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// PWM
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#define MICROPY_HW_PWM_2A (pin_P113) // D5
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#define MICROPY_HW_PWM_2B (pin_P114) // D6
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#define MICROPY_HW_PWM_3A (pin_P111) // D3
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// #define MICROPY_HW_PWM_3A (pin_P403) // PN3_6
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#define MICROPY_HW_PWM_3B (pin_P112) // D4
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// #define MICROPY_HW_PWM_3B (pin_P404) // PN3_7
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#define MICROPY_HW_PWM_4A (pin_P115) // D9
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// #define MICROPY_HW_PWM_4A (pin_P302) // H6_4
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#define MICROPY_HW_PWM_4B (pin_P608) // D7
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// #define MICROPY_HW_PWM_4B (pin_P301) // D10
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// #define MICROPY_HW_PWM_4B (pin_P204) // D13
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// #define MICROPY_HW_PWM_5A (pin_P203) // D11
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// #define MICROPY_HW_PWM_5B (pin_P202) // D12
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#define MICROPY_HW_PWM_6B (pin_P408) // PN3_8
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#define MICROPY_HW_PWM_7A (pin_P304) // H6_5
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#define MICROPY_HW_PWM_7B (pin_P303) // H6_3
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#define MICROPY_HW_PWM_8A (pin_P605) // PN4_4
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#define MICROPY_HW_PWM_8B (pin_P604) // PN4_3
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// DAC
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#define MICROPY_HW_DAC0 (pin_P014) // A4
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#define MICROPY_HW_DAC1 (pin_P015) // A5
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// Switch
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#define MICROPY_HW_HAS_SWITCH (1)
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#define MICROPY_HW_USRSW_PIN (pin_P010)
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// #define MICROPY_HW_USRSW_PIN (pin_P009)
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#define MICROPY_HW_USRSW_PULL (MP_HAL_PIN_PULL_NONE)
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#define MICROPY_HW_USRSW_EXTI_MODE (MP_HAL_PIN_TRIGGER_FALLING)
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#define MICROPY_HW_USRSW_PRESSED (0)
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// LEDs
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#define MICROPY_HW_LED1 (pin_P006)
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#define MICROPY_HW_LED2 (pin_P007)
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#define MICROPY_HW_LED3 (pin_P008)
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#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin)
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#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin)
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#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin)
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@ -0,0 +1,12 @@
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CMSIS_MCU = RA6M5
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MCU_SERIES = m33
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LD_FILES = boards/VK_RA6M5/vk_ra6m5.ld
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# MicroPython settings
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MICROPY_VFS_FAT = 1
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# FSP settings
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USE_FSP_QSPI = 1
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USE_FSP_SDHI = 1
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CFLAGS+=-DDEFAULT_DBG_CH=9
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@ -0,0 +1,166 @@
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P000,P000
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P001,P001
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P002,P002
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P003,P003
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P004,P004
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P005,P005
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P006,P006
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P007,P007
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P008,P008
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P009,P009
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P010,P010
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P014,P014
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P015,P015
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P100,P100
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P101,P101
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P102,P102
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P103,P103
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P104,P104
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P105,P105
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P106,P106
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P107,P107
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P108,P108
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P109,P109
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P110,P110
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P111,P111
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P112,P112
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P113,P113
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P114,P114
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P115,P115
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P200,P200
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P201,P201
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P202,P202
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P203,P203
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P204,P204
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P205,P205
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P206,P206
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P207,P207
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P208,P208
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P209,P209
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P210,P210
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P211,P211
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P212,P212
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P213,P213
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P214,P214
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P300,P300
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P301,P301
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P302,P302
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P303,P303
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P304,P304
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P305,P305
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P306,P306
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P307,P307
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P308,P308
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P309,P309
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P310,P310
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P311,P311
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P312,P312
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P313,P313
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P314,P314
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P315,P315
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P400,P400
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P401,P401
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P402,P402
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P403,P403
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P404,P404
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P405,P405
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P406,P406
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P407,P407
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P408,P408
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P409,P409
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P410,P410
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P411,P411
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P412,P412
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P413,P413
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P414,P414
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P415,P415
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P500,P500
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P501,P501
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P502,P502
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P503,P503
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P504,P504
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P505,P505
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P506,P506
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P507,P507
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P508,P508
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P511,P511
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P512,P512
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P513,P513
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P600,P600
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P601,P601
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P602,P602
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P603,P603
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P604,P604
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P605,P605
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P606,P606
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P607,P607
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P608,P608
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P609,P609
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P610,P610
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P611,P611
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P612,P612
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P613,P613
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P614,P614
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P615,P615
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P700,P700
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P701,P701
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P702,P702
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P703,P703
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P704,P704
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P705,P705
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P706,P706
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P707,P707
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P708,P708
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P800,P800
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P801,P801
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P802,P802
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P803,P803
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P804,P804
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P805,P805
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P806,P806
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P900,P900
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P901,P901
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P905,P905
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P906,P906
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P907,P907
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P908,P908
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PA00,PA00
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PA01,PA01
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PA08,PA08
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PA09,PA09
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PA10,PA10
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PB00,PB00
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PB01,PB01
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A0,P000
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A1,P001
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A2,P002
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A3,P003
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A4,P014
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A5,P015
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D0,P614
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D1,P613
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D2,P409
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D3,P111
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D4,P112
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D5,P113
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D6,P114
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D7,P608
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D8,P207
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D9,P115
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D10,P301
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D11,P203
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D12,P202
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D13,P204
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SW1,P010
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SW2,P009
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LED1,P006
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LED2,P007
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LED3,P008
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SDA2,P414
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SCL2,P415
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SWDIO,P108
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SWCLK,P300
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MD,P201
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LED_B,P006
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LED_G,P007
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LED_R,P008
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@ -0,0 +1,14 @@
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/* generated configuration header file - do not edit */
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#ifndef R_QSPI_CFG_H_
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#define R_QSPI_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define QSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
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#define QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM (1)
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#ifdef __cplusplus
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}
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#endif
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#endif /* R_QSPI_CFG_H_ */
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/* generated configuration header file - do not edit */
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#ifndef BOARD_CFG_H_
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#define BOARD_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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void bsp_init(void *p_args);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_CFG_H_ */
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@ -0,0 +1,62 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#include "board_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (1)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x4000)
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#define BSP_CFG_HEAP_BYTES (0x4d000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */
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@ -0,0 +1,5 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (6)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */
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@ -0,0 +1,11 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA6M5BH3CFC
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#define BSP_MCU_FEATURE_SET ('B')
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#define BSP_ROM_SIZE_BYTES (2097152)
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#define BSP_RAM_SIZE_BYTES (524288)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (176)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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@ -0,0 +1,386 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA6M5 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#if defined(_RA_TZ_SECURE)
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#define BSP_TZ_SECURE_BUILD (1)
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#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#elif defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (1)
|
||||
#else
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#endif
|
||||
|
||||
/* TrustZone Settings */
|
||||
#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
|
||||
#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
|
||||
#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
|
||||
|
||||
/* CMSIS TrustZone Settings */
|
||||
#define SCB_CSR_AIRCR_INIT (1)
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL (0)
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL (1)
|
||||
#define SCB_AIRCR_PRIS_VAL (0)
|
||||
#define TZ_FPU_NS_USAGE (1)
|
||||
#ifndef SCB_NSACR_CP10_11_VAL
|
||||
#define SCB_NSACR_CP10_11_VAL (3U)
|
||||
#endif
|
||||
|
||||
#ifndef FPU_FPCCR_TS_VAL
|
||||
#define FPU_FPCCR_TS_VAL (1U)
|
||||
#endif
|
||||
#define FPU_FPCCR_CLRONRETS_VAL (1)
|
||||
|
||||
#ifndef FPU_FPCCR_CLRONRET_VAL
|
||||
#define FPU_FPCCR_CLRONRET_VAL (1)
|
||||
#endif
|
||||
|
||||
/* The C-Cache line size that is configured during startup. */
|
||||
#ifndef BSP_CFG_C_CACHE_LINE_SIZE
|
||||
#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
|
||||
#endif
|
||||
|
||||
/* Type 1 Peripheral Security Attribution */
|
||||
|
||||
/* Peripheral Security Attribution Register (PSAR) Settings */
|
||||
#ifndef BSP_TZ_CFG_PSARB
|
||||
#define BSP_TZ_CFG_PSARB ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
|
||||
0x33f4f9) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_PSARC
|
||||
#define BSP_TZ_CFG_PSARC ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
|
||||
0x7fffcef4) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_PSARD
|
||||
#define BSP_TZ_CFG_PSARD ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
|
||||
0xffae07f0) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_PSARE
|
||||
#define BSP_TZ_CFG_PSARE ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 2) /* RTC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
|
||||
0x3f3ff8) /* Unused */
|
||||
#endif
|
||||
#ifndef BSP_TZ_CFG_MSSAR
|
||||
#define BSP_TZ_CFG_MSSAR ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
|
||||
(((3 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
|
||||
0xfffffffc) /* Unused */
|
||||
#endif
|
||||
|
||||
/* Type 2 Peripheral Security Attribution */
|
||||
|
||||
/* Security attribution for Cache registers. */
|
||||
#ifndef BSP_TZ_CFG_CSAR
|
||||
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for RSTSRn registers. */
|
||||
#ifndef BSP_TZ_CFG_RSTSAR
|
||||
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers of LVD channels. */
|
||||
#ifndef BSP_TZ_CFG_LVDSAR
|
||||
#define BSP_TZ_CFG_LVDSAR ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
|
||||
0xFFFFFFFCU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for LPM registers. */
|
||||
#ifndef BSP_TZ_CFG_LPMSAR
|
||||
#define BSP_TZ_CFG_LPMSAR ((1 > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Deep Standby Interrupt Factor Security Attribution Register. */
|
||||
#ifndef BSP_TZ_CFG_DPFSAR
|
||||
#define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for CGC registers. */
|
||||
#ifndef BSP_TZ_CFG_CGFSAR
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect all CGC registers from Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for Battery Backup registers. */
|
||||
#ifndef BSP_TZ_CFG_BBFSAR
|
||||
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARA
|
||||
#define BSP_TZ_CFG_ICUSARA ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
|
||||
0xFFFF0000U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARB
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#ifndef BSP_TZ_CFG_ICUSARC
|
||||
#define BSP_TZ_CFG_ICUSARC ( \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
|
||||
0xFFFFFF00U)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for SELSR0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARD
|
||||
#define BSP_TZ_CFG_ICUSARD ((1 > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARE
|
||||
#define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARF
|
||||
#define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
#if 3 == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
#else
|
||||
#define BSP_TZ_CFG_DTC_USED (1U)
|
||||
#endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
#ifndef BSP_TZ_CFG_FSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFEFEU)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFFFFU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
#ifndef BSP_TZ_CFG_SRAMSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR ( \
|
||||
1 | \
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
|
||||
4 | \
|
||||
0xFFFFFFF8U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
#ifndef BSP_TZ_CFG_STBRAMSAR
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
#ifndef BSP_TZ_CFG_MMPUSARA
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
#endif
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARA
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARB
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Enable Uninitialized Non-Secure Application Fallback. */
|
||||
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
|
||||
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
|
||||
#endif
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
|
||||
|
||||
/* Dual Mode Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_DUALSEL
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
|
||||
#endif
|
||||
|
||||
/* Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS0
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~(0U))
|
||||
#endif
|
||||
/* Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS1
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~(0U))
|
||||
#endif
|
||||
/* Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS2
|
||||
#define BSP_CFG_ROM_REG_BPS2 (~(0U))
|
||||
#endif
|
||||
/* Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS3
|
||||
#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS0
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~(0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS1
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~(0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS2
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (~(0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS3
|
||||
#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_PIN_CFG_H_
|
||||
#define BSP_PIN_CFG_H_
|
||||
#include "r_ioport.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
#define A0 (BSP_IO_PORT_00_PIN_00)
|
||||
#define A1 (BSP_IO_PORT_00_PIN_01)
|
||||
#define A2 (BSP_IO_PORT_00_PIN_02)
|
||||
#define A3 (BSP_IO_PORT_00_PIN_03)
|
||||
#define LED_B (BSP_IO_PORT_00_PIN_06)
|
||||
#define LED_G (BSP_IO_PORT_00_PIN_07)
|
||||
#define LED_R (BSP_IO_PORT_00_PIN_08)
|
||||
#define BTN_2 (BSP_IO_PORT_00_PIN_09)
|
||||
#define BTN_1 (BSP_IO_PORT_00_PIN_10)
|
||||
#define A4 (BSP_IO_PORT_00_PIN_14)
|
||||
#define A5 (BSP_IO_PORT_00_PIN_15)
|
||||
#define D3 (BSP_IO_PORT_01_PIN_11)
|
||||
#define D4 (BSP_IO_PORT_01_PIN_12)
|
||||
#define D5 (BSP_IO_PORT_01_PIN_13)
|
||||
#define D6 (BSP_IO_PORT_01_PIN_14)
|
||||
#define D9 (BSP_IO_PORT_01_PIN_15)
|
||||
#define D12 (BSP_IO_PORT_02_PIN_02)
|
||||
#define D11 (BSP_IO_PORT_02_PIN_03)
|
||||
#define D13 (BSP_IO_PORT_02_PIN_04)
|
||||
#define D8 (BSP_IO_PORT_02_PIN_07)
|
||||
#define D10 (BSP_IO_PORT_03_PIN_01)
|
||||
#define D2 (BSP_IO_PORT_04_PIN_09)
|
||||
#define CAN_STBY (BSP_IO_PORT_05_PIN_13)
|
||||
#define D7 (BSP_IO_PORT_06_PIN_08)
|
||||
#define D1 (BSP_IO_PORT_06_PIN_13)
|
||||
#define D0 (BSP_IO_PORT_06_PIN_14)
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* VK-RA6M5_v2.0(R7FA6M5BH3CFC).pincfg */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U, 0U) /* PLL Mul x25.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL2 Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
|
||||
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
|
||||
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
|
||||
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
|
||||
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
|
||||
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
|
||||
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/* generated common source file - do not edit */
|
||||
#include "common_data.h"
|
||||
icu_instance_ctrl_t g_external_irq14_ctrl;
|
||||
const external_irq_cfg_t g_external_irq14_cfg = { .channel = 14, .trigger =
|
||||
EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div =
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = NULL, .ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_ICU_IRQ14)
|
||||
.irq = VECTOR_NUMBER_ICU_IRQ14,
|
||||
#else
|
||||
.irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const external_irq_instance_t g_external_irq14 = { .p_ctrl =
|
||||
&g_external_irq14_ctrl, .p_cfg = &g_external_irq14_cfg, .p_api =
|
||||
&g_external_irq_on_icu };
|
||||
icu_instance_ctrl_t g_external_irq13_ctrl;
|
||||
const external_irq_cfg_t g_external_irq13_cfg = { .channel = 13, .trigger =
|
||||
EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div =
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = NULL, .ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_ICU_IRQ13)
|
||||
.irq = VECTOR_NUMBER_ICU_IRQ13,
|
||||
#else
|
||||
.irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const external_irq_instance_t g_external_irq13 = { .p_ctrl =
|
||||
&g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api =
|
||||
&g_external_irq_on_icu };
|
||||
icu_instance_ctrl_t g_external_irq7_ctrl;
|
||||
const external_irq_cfg_t g_external_irq7_cfg = { .channel = 7, .trigger =
|
||||
EXTERNAL_IRQ_TRIG_RISING, .filter_enable = false, .pclk_div =
|
||||
EXTERNAL_IRQ_PCLK_DIV_BY_64, .p_callback = callback_icu,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = NULL, .ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_ICU_IRQ7)
|
||||
.irq = VECTOR_NUMBER_ICU_IRQ7,
|
||||
#else
|
||||
.irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const external_irq_instance_t g_external_irq7 = { .p_ctrl =
|
||||
&g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api =
|
||||
&g_external_irq_on_icu };
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport = { .p_api = &g_ioport_on_ioport, .p_ctrl =
|
||||
&g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
|
||||
void g_common_init(void) {
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* generated common header file - do not edit */
|
||||
#ifndef COMMON_DATA_H_
|
||||
#define COMMON_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_icu.h"
|
||||
#include "r_external_irq_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "bsp_pin_cfg.h"
|
||||
FSP_HEADER
|
||||
/** External IRQ on ICU Instance. */
|
||||
extern const external_irq_instance_t g_external_irq14;
|
||||
|
||||
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern icu_instance_ctrl_t g_external_irq14_ctrl;
|
||||
extern const external_irq_cfg_t g_external_irq14_cfg;
|
||||
|
||||
#ifndef callback_icu
|
||||
void callback_icu(external_irq_callback_args_t *p_args);
|
||||
#endif
|
||||
/** External IRQ on ICU Instance. */
|
||||
extern const external_irq_instance_t g_external_irq13;
|
||||
|
||||
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern icu_instance_ctrl_t g_external_irq13_ctrl;
|
||||
extern const external_irq_cfg_t g_external_irq13_cfg;
|
||||
|
||||
#ifndef callback_icu
|
||||
void callback_icu(external_irq_callback_args_t *p_args);
|
||||
#endif
|
||||
/** External IRQ on ICU Instance. */
|
||||
extern const external_irq_instance_t g_external_irq7;
|
||||
|
||||
/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern icu_instance_ctrl_t g_external_irq7_ctrl;
|
||||
extern const external_irq_cfg_t g_external_irq7_cfg;
|
||||
|
||||
#ifndef callback_icu
|
||||
void callback_icu(external_irq_callback_args_t *p_args);
|
||||
#endif
|
||||
/* IOPORT Instance */
|
||||
extern const ioport_instance_t g_ioport;
|
||||
|
||||
/* IOPORT control structure. */
|
||||
extern ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
void g_common_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* COMMON_DATA_H_ */
|
||||
|
|
@ -0,0 +1,774 @@
|
|||
/* generated HAL source file - do not edit */
|
||||
#include "hal_data.h"
|
||||
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
|
||||
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
|
||||
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
|
||||
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
|
||||
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
|
||||
dtc_instance_ctrl_t g_transfer2_ctrl;
|
||||
|
||||
transfer_info_t g_transfer2_info = { .transfer_settings_word_b.dest_addr_mode =
|
||||
TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.repeat_area =
|
||||
TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq =
|
||||
TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode =
|
||||
TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode =
|
||||
TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.size =
|
||||
TRANSFER_SIZE_4_BYTE, .transfer_settings_word_b.mode =
|
||||
TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src =
|
||||
(void const *)NULL, .num_blocks = 0, .length = 128, };
|
||||
|
||||
const dtc_extended_cfg_t g_transfer2_cfg_extend = { .activation_source =
|
||||
VECTOR_NUMBER_SDHIMMC0_DMA_REQ, };
|
||||
const transfer_cfg_t g_transfer2_cfg = { .p_info = &g_transfer2_info,
|
||||
.p_extend = &g_transfer2_cfg_extend, };
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const transfer_instance_t g_transfer2 = { .p_ctrl = &g_transfer2_ctrl, .p_cfg =
|
||||
&g_transfer2_cfg, .p_api = &g_transfer_on_dtc };
|
||||
#define RA_NOT_DEFINED (UINT32_MAX)
|
||||
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
|
||||
/* If the transfer module is DMAC, define a DMAC transfer callback. */
|
||||
#include "r_dmac.h"
|
||||
extern void r_sdhi_transfer_callback(sdhi_instance_ctrl_t *p_ctrl);
|
||||
|
||||
void g_sdmmc0_dmac_callback(dmac_callback_args_t *p_args) {
|
||||
r_sdhi_transfer_callback((sdhi_instance_ctrl_t *)p_args->p_context);
|
||||
}
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
|
||||
sdhi_instance_ctrl_t g_sdmmc0_ctrl;
|
||||
sdmmc_cfg_t g_sdmmc0_cfg = { .bus_width = SDMMC_BUS_WIDTH_4_BITS, .channel = 0,
|
||||
.p_callback = sdhi_ISR, .p_context = NULL, .block_size = 512,
|
||||
.card_detect = SDMMC_CARD_DETECT_CD, .write_protect =
|
||||
SDMMC_WRITE_PROTECT_WP,
|
||||
|
||||
.p_extend = NULL, .p_lower_lvl_transfer = &g_transfer2,
|
||||
|
||||
.access_ipl = (12), .sdio_ipl = BSP_IRQ_DISABLED, .card_ipl = (12),
|
||||
.dma_req_ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_SDHIMMC0_ACCS)
|
||||
.access_irq = VECTOR_NUMBER_SDHIMMC0_ACCS,
|
||||
#else
|
||||
.access_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SDHIMMC0_CARD)
|
||||
.card_irq = VECTOR_NUMBER_SDHIMMC0_CARD,
|
||||
#else
|
||||
.card_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.sdio_irq = FSP_INVALID_VECTOR,
|
||||
#if defined(VECTOR_NUMBER_SDHIMMC0_DMA_REQ)
|
||||
.dma_req_irq = VECTOR_NUMBER_SDHIMMC0_DMA_REQ,
|
||||
#else
|
||||
.dma_req_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const sdmmc_instance_t g_sdmmc0 = { .p_ctrl = &g_sdmmc0_ctrl, .p_cfg =
|
||||
&g_sdmmc0_cfg, .p_api = &g_sdmmc_on_sdhi };
|
||||
qspi_instance_ctrl_t g_qspi0_ctrl;
|
||||
|
||||
static const spi_flash_erase_command_t g_qspi0_erase_command_list[] = {
|
||||
#if 4096 > 0
|
||||
{ .command = 0x20, .size = 4096 },
|
||||
#endif
|
||||
#if 32768 > 0
|
||||
{ .command = 0x52, .size = 32768 },
|
||||
#endif
|
||||
#if 65536 > 0
|
||||
{ .command = 0xD8, .size = 65536 },
|
||||
#endif
|
||||
#if 0xC7 > 0
|
||||
{ .command = 0xC7, .size = SPI_FLASH_ERASE_SIZE_CHIP_ERASE },
|
||||
#endif
|
||||
};
|
||||
static const qspi_extended_cfg_t g_qspi0_extended_cfg = {
|
||||
.min_qssl_deselect_cycles = QSPI_QSSL_MIN_HIGH_LEVEL_9_QSPCLK,
|
||||
.qspclk_div = QSPI_QSPCLK_DIV_2,
|
||||
};
|
||||
const spi_flash_cfg_t g_qspi0_cfg = { .spi_protocol =
|
||||
SPI_FLASH_PROTOCOL_EXTENDED_SPI, .read_mode =
|
||||
SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO, .address_bytes =
|
||||
SPI_FLASH_ADDRESS_BYTES_3, .dummy_clocks =
|
||||
SPI_FLASH_DUMMY_CLOCKS_DEFAULT, .page_program_address_lines =
|
||||
SPI_FLASH_DATA_LINES_1, .page_size_bytes = 256, .page_program_command =
|
||||
0x32, .write_enable_command = 0x06, .status_command = 0x05,
|
||||
.write_status_bit = 0, .xip_enter_command = 0x20, .xip_exit_command =
|
||||
0xFF, .p_erase_command_list = &g_qspi0_erase_command_list[0],
|
||||
.erase_command_list_length = sizeof(g_qspi0_erase_command_list)
|
||||
/ sizeof(g_qspi0_erase_command_list[0]), .p_extend =
|
||||
&g_qspi0_extended_cfg, };
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
const spi_flash_instance_t g_qspi0 = { .p_ctrl = &g_qspi0_ctrl, .p_cfg =
|
||||
&g_qspi0_cfg, .p_api = &g_qspi_on_spi_flash, };
|
||||
iic_master_instance_ctrl_t g_i2c_master2_ctrl;
|
||||
const iic_master_extended_cfg_t g_i2c_master2_extend =
|
||||
{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, .timeout_scl_low =
|
||||
IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED,
|
||||
/* Actual calculated bitrate: 98425. Actual calculated duty cycle: 50%. */ .clock_settings.brl_value =
|
||||
28, .clock_settings.brh_value = 28,
|
||||
.clock_settings.cks_value = 3, };
|
||||
const i2c_master_cfg_t g_i2c_master2_cfg = { .channel = 2, .rate =
|
||||
I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode =
|
||||
I2C_MASTER_ADDR_MODE_7BIT,
|
||||
#define RA_NOT_DEFINED (1)
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_tx = NULL,
|
||||
#else
|
||||
.p_transfer_tx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_rx = NULL,
|
||||
#else
|
||||
.p_transfer_rx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
.p_callback = callback_iic, .p_context = NULL,
|
||||
#if defined(VECTOR_NUMBER_IIC2_RXI)
|
||||
.rxi_irq = VECTOR_NUMBER_IIC2_RXI,
|
||||
#else
|
||||
.rxi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_IIC2_TXI)
|
||||
.txi_irq = VECTOR_NUMBER_IIC2_TXI,
|
||||
#else
|
||||
.txi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_IIC2_TEI)
|
||||
.tei_irq = VECTOR_NUMBER_IIC2_TEI,
|
||||
#else
|
||||
.tei_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_IIC2_ERI)
|
||||
.eri_irq = VECTOR_NUMBER_IIC2_ERI,
|
||||
#else
|
||||
.eri_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.ipl = (12), .p_extend = &g_i2c_master2_extend, };
|
||||
/* Instance structure to use this module. */
|
||||
const i2c_master_instance_t g_i2c_master2 = { .p_ctrl = &g_i2c_master2_ctrl,
|
||||
.p_cfg = &g_i2c_master2_cfg, .p_api = &g_i2c_master_on_iic };
|
||||
adc_instance_ctrl_t g_adc1_ctrl;
|
||||
const adc_extended_cfg_t g_adc1_cfg_extend = { .add_average_count = ADC_ADD_OFF,
|
||||
.clearing = ADC_CLEAR_AFTER_READ_ON, .trigger_group_b =
|
||||
ADC_TRIGGER_SYNC_ELC, .double_trigger_mode =
|
||||
ADC_DOUBLE_TRIGGER_DISABLED, .adc_vref_control =
|
||||
ADC_VREF_CONTROL_VREFH, .enable_adbuf = 0,
|
||||
#if defined(VECTOR_NUMBER_ADC1_WINDOW_A)
|
||||
.window_a_irq = VECTOR_NUMBER_ADC1_WINDOW_A,
|
||||
#else
|
||||
.window_a_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.window_a_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_ADC1_WINDOW_B)
|
||||
.window_b_irq = VECTOR_NUMBER_ADC1_WINDOW_B,
|
||||
#else
|
||||
.window_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.window_b_ipl = (BSP_IRQ_DISABLED), };
|
||||
const adc_cfg_t g_adc1_cfg = { .unit = 1, .mode = ADC_MODE_SINGLE_SCAN,
|
||||
.resolution = ADC_RESOLUTION_12_BIT, .alignment =
|
||||
(adc_alignment_t)ADC_ALIGNMENT_RIGHT, .trigger =
|
||||
ADC_TRIGGER_SOFTWARE, .p_callback = NULL,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = &g_adc1_cfg_extend,
|
||||
#if defined(VECTOR_NUMBER_ADC1_SCAN_END)
|
||||
.scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END,
|
||||
#else
|
||||
.scan_end_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.scan_end_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_ADC1_SCAN_END_B)
|
||||
.scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B,
|
||||
#else
|
||||
.scan_end_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
|
||||
#if ((0) | (0))
|
||||
const adc_window_cfg_t g_adc1_window_cfg =
|
||||
{
|
||||
.compare_mask = 0,
|
||||
.compare_mode_mask = 0,
|
||||
.compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR),
|
||||
.compare_ref_low = 0,
|
||||
.compare_ref_high = 0,
|
||||
.compare_b_channel = (ADC_WINDOW_B_CHANNEL_0),
|
||||
.compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE),
|
||||
.compare_b_ref_low = 0,
|
||||
.compare_b_ref_high = 0,
|
||||
};
|
||||
#endif
|
||||
const adc_channel_cfg_t g_adc1_channel_cfg = { .scan_mask = 0,
|
||||
.scan_mask_group_b = 0, .priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
|
||||
.add_mask = 0, .sample_hold_mask = 0, .sample_hold_states = 24,
|
||||
#if ((0) | (0))
|
||||
.p_window_cfg = (adc_window_cfg_t *)&g_adc1_window_cfg,
|
||||
#else
|
||||
.p_window_cfg = NULL,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const adc_instance_t g_adc1 = { .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg,
|
||||
.p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc };
|
||||
adc_instance_ctrl_t g_adc0_ctrl;
|
||||
const adc_extended_cfg_t g_adc0_cfg_extend = { .add_average_count = ADC_ADD_OFF,
|
||||
.clearing = ADC_CLEAR_AFTER_READ_ON, .trigger_group_b =
|
||||
ADC_TRIGGER_SYNC_ELC, .double_trigger_mode =
|
||||
ADC_DOUBLE_TRIGGER_DISABLED, .adc_vref_control =
|
||||
ADC_VREF_CONTROL_VREFH, .enable_adbuf = 0,
|
||||
#if defined(VECTOR_NUMBER_ADC0_WINDOW_A)
|
||||
.window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A,
|
||||
#else
|
||||
.window_a_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.window_a_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_ADC0_WINDOW_B)
|
||||
.window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B,
|
||||
#else
|
||||
.window_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.window_b_ipl = (BSP_IRQ_DISABLED), };
|
||||
const adc_cfg_t g_adc0_cfg = { .unit = 0, .mode = ADC_MODE_SINGLE_SCAN,
|
||||
.resolution = ADC_RESOLUTION_12_BIT, .alignment =
|
||||
(adc_alignment_t)ADC_ALIGNMENT_RIGHT, .trigger =
|
||||
ADC_TRIGGER_SOFTWARE, .p_callback = NULL,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = &g_adc0_cfg_extend,
|
||||
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
|
||||
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
|
||||
#else
|
||||
.scan_end_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.scan_end_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
|
||||
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
|
||||
#else
|
||||
.scan_end_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.scan_end_b_ipl = (BSP_IRQ_DISABLED), };
|
||||
#if ((0) | (0))
|
||||
const adc_window_cfg_t g_adc0_window_cfg =
|
||||
{
|
||||
.compare_mask = 0,
|
||||
.compare_mode_mask = 0,
|
||||
.compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR),
|
||||
.compare_ref_low = 0,
|
||||
.compare_ref_high = 0,
|
||||
.compare_b_channel = (ADC_WINDOW_B_CHANNEL_0),
|
||||
.compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE),
|
||||
.compare_b_ref_low = 0,
|
||||
.compare_b_ref_high = 0,
|
||||
};
|
||||
#endif
|
||||
const adc_channel_cfg_t g_adc0_channel_cfg = { .scan_mask = 0,
|
||||
.scan_mask_group_b = 0, .priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
|
||||
.add_mask = 0, .sample_hold_mask = 0, .sample_hold_states = 24,
|
||||
#if ((0) | (0))
|
||||
.p_window_cfg = (adc_window_cfg_t *)&g_adc0_window_cfg,
|
||||
#else
|
||||
.p_window_cfg = NULL,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const adc_instance_t g_adc0 = { .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg,
|
||||
.p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
|
||||
lpm_instance_ctrl_t g_lpm0_ctrl;
|
||||
|
||||
const lpm_cfg_t g_lpm0_cfg = { .low_power_mode = LPM_MODE_SLEEP,
|
||||
.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM
|
||||
| (lpm_standby_wake_source_t)0,
|
||||
#if BSP_FEATURE_LPM_HAS_SNOOZE
|
||||
.snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
|
||||
.snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
|
||||
.snooze_end_sources = (lpm_snooze_end_t)0,
|
||||
.dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
|
||||
#endif
|
||||
#if BSP_FEATURE_LPM_HAS_SBYCR_OPE
|
||||
.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
|
||||
#endif
|
||||
#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY
|
||||
.io_port_state = LPM_IO_PORT_NO_CHANGE,
|
||||
.power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0,
|
||||
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
|
||||
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
|
||||
#endif
|
||||
#if BSP_FEATURE_LPM_HAS_PDRAMSCR
|
||||
.ram_retention_cfg.ram_retention = (uint8_t)(0),
|
||||
.ram_retention_cfg.tcm_retention = false,
|
||||
#endif
|
||||
#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
|
||||
.ram_retention_cfg.standby_ram_retention = false,
|
||||
#endif
|
||||
#if BSP_FEATURE_LPM_HAS_LDO_CONTROL
|
||||
.ldo_standby_cfg.pll1_ldo = false,
|
||||
.ldo_standby_cfg.pll2_ldo = false,
|
||||
.ldo_standby_cfg.hoco_ldo = false,
|
||||
#endif
|
||||
.p_extend = NULL, };
|
||||
|
||||
const lpm_instance_t g_lpm0 = { .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl,
|
||||
.p_cfg = &g_lpm0_cfg };
|
||||
dtc_instance_ctrl_t g_transfer1_ctrl;
|
||||
|
||||
transfer_info_t g_transfer1_info = { .transfer_settings_word_b.dest_addr_mode =
|
||||
TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.repeat_area =
|
||||
TRANSFER_REPEAT_AREA_DESTINATION, .transfer_settings_word_b.irq =
|
||||
TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode =
|
||||
TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode =
|
||||
TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.size =
|
||||
TRANSFER_SIZE_2_BYTE, .transfer_settings_word_b.mode =
|
||||
TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src =
|
||||
(void const *)NULL, .num_blocks = 0, .length = 0, };
|
||||
|
||||
const dtc_extended_cfg_t g_transfer1_cfg_extend = { .activation_source =
|
||||
VECTOR_NUMBER_SPI0_RXI, };
|
||||
const transfer_cfg_t g_transfer1_cfg = { .p_info = &g_transfer1_info,
|
||||
.p_extend = &g_transfer1_cfg_extend, };
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const transfer_instance_t g_transfer1 = { .p_ctrl = &g_transfer1_ctrl, .p_cfg =
|
||||
&g_transfer1_cfg, .p_api = &g_transfer_on_dtc };
|
||||
dtc_instance_ctrl_t g_transfer0_ctrl;
|
||||
|
||||
transfer_info_t g_transfer0_info = { .transfer_settings_word_b.dest_addr_mode =
|
||||
TRANSFER_ADDR_MODE_FIXED, .transfer_settings_word_b.repeat_area =
|
||||
TRANSFER_REPEAT_AREA_SOURCE, .transfer_settings_word_b.irq =
|
||||
TRANSFER_IRQ_END, .transfer_settings_word_b.chain_mode =
|
||||
TRANSFER_CHAIN_MODE_DISABLED, .transfer_settings_word_b.src_addr_mode =
|
||||
TRANSFER_ADDR_MODE_INCREMENTED, .transfer_settings_word_b.size =
|
||||
TRANSFER_SIZE_2_BYTE, .transfer_settings_word_b.mode =
|
||||
TRANSFER_MODE_NORMAL, .p_dest = (void *)NULL, .p_src =
|
||||
(void const *)NULL, .num_blocks = 0, .length = 0, };
|
||||
|
||||
const dtc_extended_cfg_t g_transfer0_cfg_extend = { .activation_source =
|
||||
VECTOR_NUMBER_SPI0_TXI, };
|
||||
const transfer_cfg_t g_transfer0_cfg = { .p_info = &g_transfer0_info,
|
||||
.p_extend = &g_transfer0_cfg_extend, };
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const transfer_instance_t g_transfer0 = { .p_ctrl = &g_transfer0_ctrl, .p_cfg =
|
||||
&g_transfer0_cfg, .p_api = &g_transfer_on_dtc };
|
||||
#define RA_NOT_DEFINED (UINT32_MAX)
|
||||
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
|
||||
/* If the transfer module is DMAC, define a DMAC transfer callback. */
|
||||
#include "r_dmac.h"
|
||||
extern void spi_tx_dmac_callback(spi_instance_ctrl_t const *const p_ctrl);
|
||||
|
||||
void g_spi0_tx_transfer_callback(dmac_callback_args_t *p_args) {
|
||||
FSP_PARAMETER_NOT_USED(p_args);
|
||||
spi_tx_dmac_callback(&g_spi0_ctrl);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
|
||||
/* If the transfer module is DMAC, define a DMAC transfer callback. */
|
||||
#include "r_dmac.h"
|
||||
extern void spi_rx_dmac_callback(spi_instance_ctrl_t const *const p_ctrl);
|
||||
|
||||
void g_spi0_rx_transfer_callback(dmac_callback_args_t *p_args) {
|
||||
FSP_PARAMETER_NOT_USED(p_args);
|
||||
spi_rx_dmac_callback(&g_spi0_ctrl);
|
||||
}
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
|
||||
spi_instance_ctrl_t g_spi0_ctrl;
|
||||
|
||||
/** SPI extended configuration for SPI HAL driver */
|
||||
const spi_extended_cfg_t g_spi0_ext_cfg = { .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
|
||||
.spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, .ssl_polarity = SPI_SSLP_LOW,
|
||||
.ssl_select = SPI_SSL_SELECT_SSL0, .mosi_idle =
|
||||
SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, .parity =
|
||||
SPI_PARITY_MODE_DISABLE, .byte_swap = SPI_BYTE_SWAP_DISABLE,
|
||||
.spck_div = {
|
||||
/* Actual calculated bitrate: 12500000. */ .spbr = 3, .brdv = 0
|
||||
},
|
||||
.spck_delay = SPI_DELAY_COUNT_1,
|
||||
.ssl_negation_delay = SPI_DELAY_COUNT_1, .next_access_delay =
|
||||
SPI_DELAY_COUNT_1 };
|
||||
|
||||
/** SPI configuration for SPI HAL driver */
|
||||
const spi_cfg_t g_spi0_cfg = { .channel = 0,
|
||||
|
||||
#if defined(VECTOR_NUMBER_SPI0_RXI)
|
||||
.rxi_irq = VECTOR_NUMBER_SPI0_RXI,
|
||||
#else
|
||||
.rxi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SPI0_TXI)
|
||||
.txi_irq = VECTOR_NUMBER_SPI0_TXI,
|
||||
#else
|
||||
.txi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SPI0_TEI)
|
||||
.tei_irq = VECTOR_NUMBER_SPI0_TEI,
|
||||
#else
|
||||
.tei_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SPI0_ERI)
|
||||
.eri_irq = VECTOR_NUMBER_SPI0_ERI,
|
||||
#else
|
||||
.eri_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
|
||||
.rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
||||
|
||||
.operating_mode = SPI_MODE_MASTER,
|
||||
|
||||
.clk_phase = SPI_CLK_PHASE_EDGE_ODD, .clk_polarity =
|
||||
SPI_CLK_POLARITY_LOW,
|
||||
|
||||
.mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, .bit_order =
|
||||
SPI_BIT_ORDER_MSB_FIRST, .p_transfer_tx = g_spi0_P_TRANSFER_TX,
|
||||
.p_transfer_rx = g_spi0_P_TRANSFER_RX, .p_callback = spi_callback,
|
||||
|
||||
.p_context = NULL, .p_extend = (void *)&g_spi0_ext_cfg, };
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const spi_instance_t g_spi0 = { .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg,
|
||||
.p_api = &g_spi_on_spi };
|
||||
agt_instance_ctrl_t g_timer1_ctrl;
|
||||
const agt_extended_cfg_t g_timer1_extend =
|
||||
{ .count_source = AGT_CLOCK_PCLKB, .agto = AGT_PIN_CFG_DISABLED,
|
||||
.agtoab_settings_b.agtoa = AGT_PIN_CFG_DISABLED,
|
||||
.agtoab_settings_b.agtob = AGT_PIN_CFG_DISABLED,
|
||||
.measurement_mode = AGT_MEASURE_DISABLED, .agtio_filter =
|
||||
AGT_AGTIO_FILTER_NONE, .enable_pin =
|
||||
AGT_ENABLE_PIN_NOT_USED, .trigger_edge =
|
||||
AGT_TRIGGER_EDGE_RISING, };
|
||||
const timer_cfg_t g_timer1_cfg = { .mode = TIMER_MODE_PERIODIC,
|
||||
/* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts =
|
||||
(uint32_t)0x10000, .duty_cycle_counts = 0x8000, .source_div =
|
||||
(timer_source_div_t)0, .channel = 1, .p_callback = callback_agt,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = &g_timer1_extend, .cycle_end_ipl = (5),
|
||||
#if defined(VECTOR_NUMBER_AGT1_INT)
|
||||
.cycle_end_irq = VECTOR_NUMBER_AGT1_INT,
|
||||
#else
|
||||
.cycle_end_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const timer_instance_t g_timer1 = { .p_ctrl = &g_timer1_ctrl, .p_cfg =
|
||||
&g_timer1_cfg, .p_api = &g_timer_on_agt };
|
||||
agt_instance_ctrl_t g_timer0_ctrl;
|
||||
const agt_extended_cfg_t g_timer0_extend =
|
||||
{ .count_source = AGT_CLOCK_PCLKB, .agto = AGT_PIN_CFG_DISABLED,
|
||||
.agtoab_settings_b.agtoa = AGT_PIN_CFG_DISABLED,
|
||||
.agtoab_settings_b.agtob = AGT_PIN_CFG_DISABLED,
|
||||
.measurement_mode = AGT_MEASURE_DISABLED, .agtio_filter =
|
||||
AGT_AGTIO_FILTER_NONE, .enable_pin =
|
||||
AGT_ENABLE_PIN_NOT_USED, .trigger_edge =
|
||||
AGT_TRIGGER_EDGE_RISING, };
|
||||
const timer_cfg_t g_timer0_cfg = { .mode = TIMER_MODE_PERIODIC,
|
||||
/* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts =
|
||||
(uint32_t)0x10000, .duty_cycle_counts = 0x8000, .source_div =
|
||||
(timer_source_div_t)0, .channel = 0, .p_callback = callback_agt,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = &g_timer0_extend, .cycle_end_ipl = (5),
|
||||
#if defined(VECTOR_NUMBER_AGT0_INT)
|
||||
.cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
|
||||
#else
|
||||
.cycle_end_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const timer_instance_t g_timer0 = { .p_ctrl = &g_timer0_ctrl, .p_cfg =
|
||||
&g_timer0_cfg, .p_api = &g_timer_on_agt };
|
||||
flash_hp_instance_ctrl_t g_flash0_ctrl;
|
||||
const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL,
|
||||
.p_context = NULL,
|
||||
#if defined(VECTOR_NUMBER_FCU_FRDYI)
|
||||
.irq = VECTOR_NUMBER_FCU_FRDYI,
|
||||
#else
|
||||
.irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_FCU_FIFERR)
|
||||
.err_irq = VECTOR_NUMBER_FCU_FIFERR,
|
||||
#else
|
||||
.err_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.err_ipl = (BSP_IRQ_DISABLED), .ipl = (BSP_IRQ_DISABLED), };
|
||||
/* Instance structure to use this module. */
|
||||
const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg =
|
||||
&g_flash0_cfg, .p_api = &g_flash_on_flash_hp };
|
||||
rtc_instance_ctrl_t g_rtc0_ctrl;
|
||||
const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = { .adjustment_mode =
|
||||
RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, .adjustment_period =
|
||||
RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, .adjustment_type =
|
||||
RTC_ERROR_ADJUSTMENT_NONE, .adjustment_value = 0, };
|
||||
const rtc_cfg_t g_rtc0_cfg = { .clock_source = RTC_CLOCK_SOURCE_LOCO,
|
||||
.freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg,
|
||||
.p_callback = NULL, .p_context = NULL, .alarm_ipl = (14),
|
||||
.periodic_ipl = (14), .carry_ipl = (14),
|
||||
#if defined(VECTOR_NUMBER_RTC_ALARM)
|
||||
.alarm_irq = VECTOR_NUMBER_RTC_ALARM,
|
||||
#else
|
||||
.alarm_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_RTC_PERIOD)
|
||||
.periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
|
||||
#else
|
||||
.periodic_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_RTC_CARRY)
|
||||
.carry_irq = VECTOR_NUMBER_RTC_CARRY,
|
||||
#else
|
||||
.carry_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const rtc_instance_t g_rtc0 = { .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg,
|
||||
.p_api = &g_rtc_on_rtc };
|
||||
sci_uart_instance_ctrl_t g_uart9_ctrl;
|
||||
|
||||
baud_setting_t g_uart9_baud_setting = {
|
||||
/* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0,
|
||||
.semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1,
|
||||
.cks = 0, .brr = 53, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme =
|
||||
false
|
||||
};
|
||||
|
||||
/** UART extended configuration for UARTonSCI HAL driver */
|
||||
const sci_uart_extended_cfg_t g_uart9_cfg_extend = {
|
||||
.clock = SCI_UART_CLOCK_INT, .rx_edge_start =
|
||||
SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel =
|
||||
SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger =
|
||||
SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting =
|
||||
&g_uart9_baud_setting,
|
||||
.flow_control = SCI_UART_FLOW_CONTROL_RTS,
|
||||
#if 0xFF != 0xFF
|
||||
.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
|
||||
#endif
|
||||
.rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity =
|
||||
SCI_UART_RS485_DE_POLARITY_HIGH,
|
||||
#if 0xFF != 0xFF
|
||||
.de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.de_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
/** UART interface configuration */
|
||||
const uart_cfg_t g_uart9_cfg = { .channel = 9, .data_bits = UART_DATA_BITS_8,
|
||||
.parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
|
||||
user_uart_callback, .p_context = NULL, .p_extend =
|
||||
&g_uart9_cfg_extend,
|
||||
#define RA_NOT_DEFINED (1)
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_tx = NULL,
|
||||
#else
|
||||
.p_transfer_tx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_rx = NULL,
|
||||
#else
|
||||
.p_transfer_rx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
.rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_SCI9_RXI)
|
||||
.rxi_irq = VECTOR_NUMBER_SCI9_RXI,
|
||||
#else
|
||||
.rxi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI9_TXI)
|
||||
.txi_irq = VECTOR_NUMBER_SCI9_TXI,
|
||||
#else
|
||||
.txi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI9_TEI)
|
||||
.tei_irq = VECTOR_NUMBER_SCI9_TEI,
|
||||
#else
|
||||
.tei_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI9_ERI)
|
||||
.eri_irq = VECTOR_NUMBER_SCI9_ERI,
|
||||
#else
|
||||
.eri_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const uart_instance_t g_uart9 = { .p_ctrl = &g_uart9_ctrl,
|
||||
.p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci };
|
||||
sci_uart_instance_ctrl_t g_uart7_ctrl;
|
||||
|
||||
baud_setting_t g_uart7_baud_setting = {
|
||||
/* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0,
|
||||
.semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1,
|
||||
.cks = 0, .brr = 53, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme =
|
||||
false
|
||||
};
|
||||
|
||||
/** UART extended configuration for UARTonSCI HAL driver */
|
||||
const sci_uart_extended_cfg_t g_uart7_cfg_extend = {
|
||||
.clock = SCI_UART_CLOCK_INT, .rx_edge_start =
|
||||
SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel =
|
||||
SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger =
|
||||
SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting =
|
||||
&g_uart7_baud_setting,
|
||||
.flow_control = SCI_UART_FLOW_CONTROL_RTS,
|
||||
#if 0xFF != 0xFF
|
||||
.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
|
||||
#endif
|
||||
.rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity =
|
||||
SCI_UART_RS485_DE_POLARITY_HIGH,
|
||||
#if 0xFF != 0xFF
|
||||
.de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.de_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
/** UART interface configuration */
|
||||
const uart_cfg_t g_uart7_cfg = { .channel = 7, .data_bits = UART_DATA_BITS_8,
|
||||
.parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
|
||||
user_uart_callback, .p_context = NULL, .p_extend =
|
||||
&g_uart7_cfg_extend,
|
||||
#define RA_NOT_DEFINED (1)
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_tx = NULL,
|
||||
#else
|
||||
.p_transfer_tx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_rx = NULL,
|
||||
#else
|
||||
.p_transfer_rx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
.rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_SCI7_RXI)
|
||||
.rxi_irq = VECTOR_NUMBER_SCI7_RXI,
|
||||
#else
|
||||
.rxi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI7_TXI)
|
||||
.txi_irq = VECTOR_NUMBER_SCI7_TXI,
|
||||
#else
|
||||
.txi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI7_TEI)
|
||||
.tei_irq = VECTOR_NUMBER_SCI7_TEI,
|
||||
#else
|
||||
.tei_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI7_ERI)
|
||||
.eri_irq = VECTOR_NUMBER_SCI7_ERI,
|
||||
#else
|
||||
.eri_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const uart_instance_t g_uart7 = { .p_ctrl = &g_uart7_ctrl,
|
||||
.p_cfg = &g_uart7_cfg, .p_api = &g_uart_on_sci };
|
||||
sci_uart_instance_ctrl_t g_uart6_ctrl;
|
||||
|
||||
baud_setting_t g_uart6_baud_setting = {
|
||||
/* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0,
|
||||
.semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1,
|
||||
.cks = 0, .brr = 53, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme =
|
||||
false
|
||||
};
|
||||
|
||||
/** UART extended configuration for UARTonSCI HAL driver */
|
||||
const sci_uart_extended_cfg_t g_uart6_cfg_extend = {
|
||||
.clock = SCI_UART_CLOCK_INT, .rx_edge_start =
|
||||
SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel =
|
||||
SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger =
|
||||
SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting =
|
||||
&g_uart6_baud_setting,
|
||||
.flow_control = SCI_UART_FLOW_CONTROL_RTS,
|
||||
#if 0xFF != 0xFF
|
||||
.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
|
||||
#endif
|
||||
.rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity =
|
||||
SCI_UART_RS485_DE_POLARITY_HIGH,
|
||||
#if 0xFF != 0xFF
|
||||
.de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.de_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
/** UART interface configuration */
|
||||
const uart_cfg_t g_uart6_cfg = { .channel = 6, .data_bits = UART_DATA_BITS_8,
|
||||
.parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
|
||||
user_uart_callback, .p_context = NULL, .p_extend =
|
||||
&g_uart6_cfg_extend,
|
||||
#define RA_NOT_DEFINED (1)
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_tx = NULL,
|
||||
#else
|
||||
.p_transfer_tx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_rx = NULL,
|
||||
#else
|
||||
.p_transfer_rx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
.rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_SCI6_RXI)
|
||||
.rxi_irq = VECTOR_NUMBER_SCI6_RXI,
|
||||
#else
|
||||
.rxi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI6_TXI)
|
||||
.txi_irq = VECTOR_NUMBER_SCI6_TXI,
|
||||
#else
|
||||
.txi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI6_TEI)
|
||||
.tei_irq = VECTOR_NUMBER_SCI6_TEI,
|
||||
#else
|
||||
.tei_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI6_ERI)
|
||||
.eri_irq = VECTOR_NUMBER_SCI6_ERI,
|
||||
#else
|
||||
.eri_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const uart_instance_t g_uart6 = { .p_ctrl = &g_uart6_ctrl,
|
||||
.p_cfg = &g_uart6_cfg, .p_api = &g_uart_on_sci };
|
||||
void g_hal_init(void) {
|
||||
g_common_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
/* generated HAL header file - do not edit */
|
||||
#ifndef HAL_DATA_H_
|
||||
#define HAL_DATA_H_
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "common_data.h"
|
||||
#include "r_dtc.h"
|
||||
#include "r_transfer_api.h"
|
||||
#include "r_sdhi.h"
|
||||
#include "r_sdmmc_api.h"
|
||||
#include "r_qspi.h"
|
||||
#include "r_spi_flash_api.h"
|
||||
#include "r_iic_master.h"
|
||||
#include "r_i2c_master_api.h"
|
||||
#include "r_adc.h"
|
||||
#include "r_adc_api.h"
|
||||
#include "r_lpm.h"
|
||||
#include "r_lpm_api.h"
|
||||
#include "r_spi.h"
|
||||
#include "r_agt.h"
|
||||
#include "r_timer_api.h"
|
||||
#include "r_flash_hp.h"
|
||||
#include "r_flash_api.h"
|
||||
#include "r_rtc.h"
|
||||
#include "r_rtc_api.h"
|
||||
#include "r_sci_uart.h"
|
||||
#include "r_uart_api.h"
|
||||
FSP_HEADER
|
||||
/* Transfer on DTC Instance. */
|
||||
extern const transfer_instance_t g_transfer2;
|
||||
|
||||
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern dtc_instance_ctrl_t g_transfer2_ctrl;
|
||||
extern const transfer_cfg_t g_transfer2_cfg;
|
||||
/** SDMMC on SDMMC Instance. */
|
||||
extern const sdmmc_instance_t g_sdmmc0;
|
||||
|
||||
/** Access the SDMMC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern sdhi_instance_ctrl_t g_sdmmc0_ctrl;
|
||||
extern sdmmc_cfg_t g_sdmmc0_cfg;
|
||||
|
||||
#ifndef sdhi_ISR
|
||||
void sdhi_ISR(sdmmc_callback_args_t *p_args);
|
||||
#endif
|
||||
extern const spi_flash_instance_t g_qspi0;
|
||||
extern qspi_instance_ctrl_t g_qspi0_ctrl;
|
||||
extern const spi_flash_cfg_t g_qspi0_cfg;
|
||||
/* I2C Master on IIC Instance. */
|
||||
extern const i2c_master_instance_t g_i2c_master2;
|
||||
|
||||
/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern iic_master_instance_ctrl_t g_i2c_master2_ctrl;
|
||||
extern const i2c_master_cfg_t g_i2c_master2_cfg;
|
||||
|
||||
#ifndef callback_iic
|
||||
void callback_iic(i2c_master_callback_args_t *p_args);
|
||||
#endif
|
||||
/** ADC on ADC Instance. */
|
||||
extern const adc_instance_t g_adc1;
|
||||
|
||||
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern adc_instance_ctrl_t g_adc1_ctrl;
|
||||
extern const adc_cfg_t g_adc1_cfg;
|
||||
extern const adc_channel_cfg_t g_adc1_channel_cfg;
|
||||
|
||||
#ifndef NULL
|
||||
void NULL(adc_callback_args_t *p_args);
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 0
|
||||
#endif
|
||||
/** ADC on ADC Instance. */
|
||||
extern const adc_instance_t g_adc0;
|
||||
|
||||
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern adc_instance_ctrl_t g_adc0_ctrl;
|
||||
extern const adc_cfg_t g_adc0_cfg;
|
||||
extern const adc_channel_cfg_t g_adc0_channel_cfg;
|
||||
|
||||
#ifndef NULL
|
||||
void NULL(adc_callback_args_t *p_args);
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 0
|
||||
#endif
|
||||
/** lpm Instance */
|
||||
extern const lpm_instance_t g_lpm0;
|
||||
|
||||
/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern lpm_instance_ctrl_t g_lpm0_ctrl;
|
||||
extern const lpm_cfg_t g_lpm0_cfg;
|
||||
/* Transfer on DTC Instance. */
|
||||
extern const transfer_instance_t g_transfer1;
|
||||
|
||||
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern dtc_instance_ctrl_t g_transfer1_ctrl;
|
||||
extern const transfer_cfg_t g_transfer1_cfg;
|
||||
/* Transfer on DTC Instance. */
|
||||
extern const transfer_instance_t g_transfer0;
|
||||
|
||||
/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern dtc_instance_ctrl_t g_transfer0_ctrl;
|
||||
extern const transfer_cfg_t g_transfer0_cfg;
|
||||
/** SPI on SPI Instance. */
|
||||
extern const spi_instance_t g_spi0;
|
||||
|
||||
/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern spi_instance_ctrl_t g_spi0_ctrl;
|
||||
extern const spi_cfg_t g_spi0_cfg;
|
||||
|
||||
/** Callback used by SPI Instance. */
|
||||
#ifndef spi_callback
|
||||
void spi_callback(spi_callback_args_t *p_args);
|
||||
#endif
|
||||
|
||||
#define RA_NOT_DEFINED (1)
|
||||
#if (RA_NOT_DEFINED == g_transfer0)
|
||||
#define g_spi0_P_TRANSFER_TX (NULL)
|
||||
#else
|
||||
#define g_spi0_P_TRANSFER_TX (&g_transfer0)
|
||||
#endif
|
||||
#if (RA_NOT_DEFINED == g_transfer1)
|
||||
#define g_spi0_P_TRANSFER_RX (NULL)
|
||||
#else
|
||||
#define g_spi0_P_TRANSFER_RX (&g_transfer1)
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
/** AGT Timer Instance */
|
||||
extern const timer_instance_t g_timer1;
|
||||
|
||||
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern agt_instance_ctrl_t g_timer1_ctrl;
|
||||
extern const timer_cfg_t g_timer1_cfg;
|
||||
|
||||
#ifndef callback_agt
|
||||
void callback_agt(timer_callback_args_t *p_args);
|
||||
#endif
|
||||
/** AGT Timer Instance */
|
||||
extern const timer_instance_t g_timer0;
|
||||
|
||||
/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern agt_instance_ctrl_t g_timer0_ctrl;
|
||||
extern const timer_cfg_t g_timer0_cfg;
|
||||
|
||||
#ifndef callback_agt
|
||||
void callback_agt(timer_callback_args_t *p_args);
|
||||
#endif
|
||||
/* Flash on Flash HP Instance */
|
||||
extern const flash_instance_t g_flash0;
|
||||
|
||||
/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern flash_hp_instance_ctrl_t g_flash0_ctrl;
|
||||
extern const flash_cfg_t g_flash0_cfg;
|
||||
|
||||
#ifndef NULL
|
||||
void NULL(flash_callback_args_t *p_args);
|
||||
#endif
|
||||
/* RTC Instance. */
|
||||
extern const rtc_instance_t g_rtc0;
|
||||
|
||||
/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern rtc_instance_ctrl_t g_rtc0_ctrl;
|
||||
extern const rtc_cfg_t g_rtc0_cfg;
|
||||
|
||||
#ifndef NULL
|
||||
void NULL(rtc_callback_args_t *p_args);
|
||||
#endif
|
||||
/** UART on SCI Instance. */
|
||||
extern const uart_instance_t g_uart9;
|
||||
|
||||
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern sci_uart_instance_ctrl_t g_uart9_ctrl;
|
||||
extern const uart_cfg_t g_uart9_cfg;
|
||||
extern const sci_uart_extended_cfg_t g_uart9_cfg_extend;
|
||||
|
||||
#ifndef user_uart_callback
|
||||
void user_uart_callback(uart_callback_args_t *p_args);
|
||||
#endif
|
||||
/** UART on SCI Instance. */
|
||||
extern const uart_instance_t g_uart7;
|
||||
|
||||
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern sci_uart_instance_ctrl_t g_uart7_ctrl;
|
||||
extern const uart_cfg_t g_uart7_cfg;
|
||||
extern const sci_uart_extended_cfg_t g_uart7_cfg_extend;
|
||||
|
||||
#ifndef user_uart_callback
|
||||
void user_uart_callback(uart_callback_args_t *p_args);
|
||||
#endif
|
||||
/** UART on SCI Instance. */
|
||||
extern const uart_instance_t g_uart6;
|
||||
|
||||
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern sci_uart_instance_ctrl_t g_uart6_ctrl;
|
||||
extern const uart_cfg_t g_uart6_cfg;
|
||||
extern const sci_uart_extended_cfg_t g_uart6_cfg_extend;
|
||||
|
||||
#ifndef user_uart_callback
|
||||
void user_uart_callback(uart_callback_args_t *p_args);
|
||||
#endif
|
||||
void g_hal_init(void);
|
||||
FSP_FOOTER
|
||||
#endif /* HAL_DATA_H_ */
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/* generated pin source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport_api.h"
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { { .pin = BSP_IO_PORT_00_PIN_00,
|
||||
.pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
|
||||
{ .pin = BSP_IO_PORT_00_PIN_01, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_02, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_03, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
|
||||
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_07, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
|
||||
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_08, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT
|
||||
| (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_09, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_IRQ_ENABLE
|
||||
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, {
|
||||
.pin = BSP_IO_PORT_00_PIN_10, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_IRQ_ENABLE
|
||||
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT)
|
||||
},
|
||||
{ .pin = BSP_IO_PORT_00_PIN_14, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin =
|
||||
BSP_IO_PORT_00_PIN_15, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_00, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_01, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_02, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_03, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_04, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_05, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_07, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_08, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_09, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin =
|
||||
BSP_IO_PORT_01_PIN_10, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin =
|
||||
BSP_IO_PORT_02_PIN_05, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_02_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_02_PIN_09, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_02_PIN_10, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_00, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_05, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_07, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_08, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_09, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin =
|
||||
BSP_IO_PORT_03_PIN_10, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_QSPI) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_01, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_02, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_05, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_07, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_10, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_DRIVE_MID
|
||||
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_11, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_12, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_13, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SDHI_MMC) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_14, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_DRIVE_MID
|
||||
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_IIC) }, { .pin =
|
||||
BSP_IO_PORT_04_PIN_15, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_DRIVE_MID
|
||||
| (uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_IIC) }, { .pin =
|
||||
BSP_IO_PORT_05_PIN_05, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, { .pin =
|
||||
BSP_IO_PORT_05_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, { .pin =
|
||||
BSP_IO_PORT_05_PIN_11, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_CAN) }, { .pin =
|
||||
BSP_IO_PORT_05_PIN_12, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_CAN) }, { .pin =
|
||||
BSP_IO_PORT_06_PIN_00, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_06_PIN_01, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_06_PIN_02, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_06_PIN_10, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_OSPI) }, { .pin =
|
||||
BSP_IO_PORT_06_PIN_13, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin =
|
||||
BSP_IO_PORT_06_PIN_14, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_00, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_01, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_02, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_03, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_04, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_05, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_ETHER_RMII) }, { .pin =
|
||||
BSP_IO_PORT_07_PIN_06, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_IRQ_ENABLE
|
||||
| (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, {
|
||||
.pin = BSP_IO_PORT_11_PIN_01, .pin_cfg =
|
||||
((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
|
||||
| (uint32_t)IOPORT_PERIPHERAL_USB_HS)
|
||||
}, };
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = { .number_of_pins =
|
||||
sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data =
|
||||
&g_bsp_pin_cfg_data[0], };
|
||||
|
||||
#if BSP_TZ_SECURE_BUILD
|
||||
|
||||
void R_BSP_PinCfgSecurityInit(void);
|
||||
|
||||
/* Initialize SAR registers for secure pins. */
|
||||
void R_BSP_PinCfgSecurityInit(void) {
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#else
|
||||
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
|
||||
#endif
|
||||
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
|
||||
|
||||
|
||||
for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
|
||||
{
|
||||
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
|
||||
uint32_t port = port_pin >> 8U;
|
||||
uint32_t pin = port_pin & 0xFFU;
|
||||
pmsar[port] &= (uint16_t) ~(1U << pin);
|
||||
}
|
||||
|
||||
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
|
||||
{
|
||||
#if (2U == BSP_FEATURE_IOPORT_VERSION)
|
||||
R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i];
|
||||
#else
|
||||
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/* generated vector source file - do not edit */
|
||||
#include "bsp_api.h"
|
||||
/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
|
||||
#if VECTOR_DATA_IRQ_COUNT > 0
|
||||
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
|
||||
{
|
||||
[0] = sci_uart_rxi_isr, /* SCI6 RXI (Received data full) */
|
||||
[1] = sci_uart_txi_isr, /* SCI6 TXI (Transmit data empty) */
|
||||
[2] = sci_uart_tei_isr, /* SCI6 TEI (Transmit end) */
|
||||
[3] = sci_uart_eri_isr, /* SCI6 ERI (Receive error) */
|
||||
[4] = sci_uart_rxi_isr, /* SCI7 RXI (Received data full) */
|
||||
[5] = sci_uart_txi_isr, /* SCI7 TXI (Transmit data empty) */
|
||||
[6] = sci_uart_tei_isr, /* SCI7 TEI (Transmit end) */
|
||||
[7] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */
|
||||
[8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */
|
||||
[9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
|
||||
[10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
|
||||
[11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
|
||||
[12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */
|
||||
[13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */
|
||||
[14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */
|
||||
[15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */
|
||||
[16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */
|
||||
[17] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */
|
||||
[18] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */
|
||||
[19] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */
|
||||
[20] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */
|
||||
[21] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */
|
||||
[22] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */
|
||||
[23] = spi_eri_isr, /* SPI0 ERI (Error) */
|
||||
[24] = iic_master_rxi_isr, /* IIC2 RXI (Receive data full) */
|
||||
[25] = iic_master_txi_isr, /* IIC2 TXI (Transmit data empty) */
|
||||
[26] = iic_master_tei_isr, /* IIC2 TEI (Transmit end) */
|
||||
[27] = iic_master_eri_isr, /* IIC2 ERI (Transfer error) */
|
||||
[28] = sdhimmc_accs_isr, /* SDHIMMC0 ACCS (Card access) */
|
||||
[29] = sdhimmc_card_isr, /* SDHIMMC0 CARD (Card detect) */
|
||||
[30] = sdhimmc_dma_req_isr, /* SDHIMMC0 DMA REQ (DMA transfer request) */
|
||||
};
|
||||
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
|
||||
{
|
||||
[0] = BSP_PRV_IELS_ENUM(EVENT_SCI6_RXI), /* SCI6 RXI (Received data full) */
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_SCI6_TXI), /* SCI6 TXI (Transmit data empty) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_SCI6_TEI), /* SCI6 TEI (Transmit end) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_SCI6_ERI), /* SCI6 ERI (Receive error) */
|
||||
[4] = BSP_PRV_IELS_ENUM(EVENT_SCI7_RXI), /* SCI7 RXI (Received data full) */
|
||||
[5] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TXI), /* SCI7 TXI (Transmit data empty) */
|
||||
[6] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TEI), /* SCI7 TEI (Transmit end) */
|
||||
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */
|
||||
[8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */
|
||||
[9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
|
||||
[10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
|
||||
[11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
|
||||
[12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */
|
||||
[13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */
|
||||
[14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */
|
||||
[15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */
|
||||
[16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */
|
||||
[17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */
|
||||
[18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */
|
||||
[19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ14), /* ICU IRQ14 (External pin interrupt 14) */
|
||||
[20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */
|
||||
[21] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */
|
||||
[22] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */
|
||||
[23] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */
|
||||
[24] = BSP_PRV_IELS_ENUM(EVENT_IIC2_RXI), /* IIC2 RXI (Receive data full) */
|
||||
[25] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TXI), /* IIC2 TXI (Transmit data empty) */
|
||||
[26] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TEI), /* IIC2 TEI (Transmit end) */
|
||||
[27] = BSP_PRV_IELS_ENUM(EVENT_IIC2_ERI), /* IIC2 ERI (Transfer error) */
|
||||
[28] = BSP_PRV_IELS_ENUM(EVENT_SDHIMMC0_ACCS), /* SDHIMMC0 ACCS (Card access) */
|
||||
[29] = BSP_PRV_IELS_ENUM(EVENT_SDHIMMC0_CARD), /* SDHIMMC0 CARD (Card detect) */
|
||||
[30] = BSP_PRV_IELS_ENUM(EVENT_SDHIMMC0_DMA_REQ), /* SDHIMMC0 DMA REQ (DMA transfer request) */
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/* generated vector header file - do not edit */
|
||||
#ifndef VECTOR_DATA_H
|
||||
#define VECTOR_DATA_H
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Number of interrupts allocated */
|
||||
#ifndef VECTOR_DATA_IRQ_COUNT
|
||||
#define VECTOR_DATA_IRQ_COUNT (31)
|
||||
#endif
|
||||
/* ISR prototypes */
|
||||
void sci_uart_rxi_isr(void);
|
||||
void sci_uart_txi_isr(void);
|
||||
void sci_uart_tei_isr(void);
|
||||
void sci_uart_eri_isr(void);
|
||||
void rtc_alarm_periodic_isr(void);
|
||||
void rtc_carry_isr(void);
|
||||
void agt_int_isr(void);
|
||||
void r_icu_isr(void);
|
||||
void spi_rxi_isr(void);
|
||||
void spi_txi_isr(void);
|
||||
void spi_tei_isr(void);
|
||||
void spi_eri_isr(void);
|
||||
void iic_master_rxi_isr(void);
|
||||
void iic_master_txi_isr(void);
|
||||
void iic_master_tei_isr(void);
|
||||
void iic_master_eri_isr(void);
|
||||
void sdhimmc_accs_isr(void);
|
||||
void sdhimmc_card_isr(void);
|
||||
void sdhimmc_dma_req_isr(void);
|
||||
|
||||
/* Vector table allocations */
|
||||
#define VECTOR_NUMBER_SCI6_RXI ((IRQn_Type)0) /* SCI6 RXI (Received data full) */
|
||||
#define SCI6_RXI_IRQn ((IRQn_Type)0) /* SCI6 RXI (Received data full) */
|
||||
#define VECTOR_NUMBER_SCI6_TXI ((IRQn_Type)1) /* SCI6 TXI (Transmit data empty) */
|
||||
#define SCI6_TXI_IRQn ((IRQn_Type)1) /* SCI6 TXI (Transmit data empty) */
|
||||
#define VECTOR_NUMBER_SCI6_TEI ((IRQn_Type)2) /* SCI6 TEI (Transmit end) */
|
||||
#define SCI6_TEI_IRQn ((IRQn_Type)2) /* SCI6 TEI (Transmit end) */
|
||||
#define VECTOR_NUMBER_SCI6_ERI ((IRQn_Type)3) /* SCI6 ERI (Receive error) */
|
||||
#define SCI6_ERI_IRQn ((IRQn_Type)3) /* SCI6 ERI (Receive error) */
|
||||
#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type)4) /* SCI7 RXI (Received data full) */
|
||||
#define SCI7_RXI_IRQn ((IRQn_Type)4) /* SCI7 RXI (Received data full) */
|
||||
#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */
|
||||
#define SCI7_TXI_IRQn ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */
|
||||
#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */
|
||||
#define SCI7_TEI_IRQn ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */
|
||||
#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type)7) /* SCI7 ERI (Receive error) */
|
||||
#define SCI7_ERI_IRQn ((IRQn_Type)7) /* SCI7 ERI (Receive error) */
|
||||
#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
|
||||
#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */
|
||||
#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
|
||||
#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */
|
||||
#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
|
||||
#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */
|
||||
#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
|
||||
#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */
|
||||
#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
|
||||
#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */
|
||||
#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
|
||||
#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */
|
||||
#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
|
||||
#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */
|
||||
#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
|
||||
#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */
|
||||
#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */
|
||||
#define AGT1_INT_IRQn ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */
|
||||
#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)17) /* ICU IRQ7 (External pin interrupt 7) */
|
||||
#define ICU_IRQ7_IRQn ((IRQn_Type)17) /* ICU IRQ7 (External pin interrupt 7) */
|
||||
#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)18) /* ICU IRQ13 (External pin interrupt 13) */
|
||||
#define ICU_IRQ13_IRQn ((IRQn_Type)18) /* ICU IRQ13 (External pin interrupt 13) */
|
||||
#define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type)19) /* ICU IRQ14 (External pin interrupt 14) */
|
||||
#define ICU_IRQ14_IRQn ((IRQn_Type)19) /* ICU IRQ14 (External pin interrupt 14) */
|
||||
#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)20) /* SPI0 RXI (Receive buffer full) */
|
||||
#define SPI0_RXI_IRQn ((IRQn_Type)20) /* SPI0 RXI (Receive buffer full) */
|
||||
#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)21) /* SPI0 TXI (Transmit buffer empty) */
|
||||
#define SPI0_TXI_IRQn ((IRQn_Type)21) /* SPI0 TXI (Transmit buffer empty) */
|
||||
#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)22) /* SPI0 TEI (Transmission complete event) */
|
||||
#define SPI0_TEI_IRQn ((IRQn_Type)22) /* SPI0 TEI (Transmission complete event) */
|
||||
#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)23) /* SPI0 ERI (Error) */
|
||||
#define SPI0_ERI_IRQn ((IRQn_Type)23) /* SPI0 ERI (Error) */
|
||||
#define VECTOR_NUMBER_IIC2_RXI ((IRQn_Type)24) /* IIC2 RXI (Receive data full) */
|
||||
#define IIC2_RXI_IRQn ((IRQn_Type)24) /* IIC2 RXI (Receive data full) */
|
||||
#define VECTOR_NUMBER_IIC2_TXI ((IRQn_Type)25) /* IIC2 TXI (Transmit data empty) */
|
||||
#define IIC2_TXI_IRQn ((IRQn_Type)25) /* IIC2 TXI (Transmit data empty) */
|
||||
#define VECTOR_NUMBER_IIC2_TEI ((IRQn_Type)26) /* IIC2 TEI (Transmit end) */
|
||||
#define IIC2_TEI_IRQn ((IRQn_Type)26) /* IIC2 TEI (Transmit end) */
|
||||
#define VECTOR_NUMBER_IIC2_ERI ((IRQn_Type)27) /* IIC2 ERI (Transfer error) */
|
||||
#define IIC2_ERI_IRQn ((IRQn_Type)27) /* IIC2 ERI (Transfer error) */
|
||||
#define VECTOR_NUMBER_SDHIMMC0_ACCS ((IRQn_Type)28) /* SDHIMMC0 ACCS (Card access) */
|
||||
#define SDHIMMC0_ACCS_IRQn ((IRQn_Type)28) /* SDHIMMC0 ACCS (Card access) */
|
||||
#define VECTOR_NUMBER_SDHIMMC0_CARD ((IRQn_Type)29) /* SDHIMMC0 CARD (Card detect) */
|
||||
#define SDHIMMC0_CARD_IRQn ((IRQn_Type)29) /* SDHIMMC0 CARD (Card detect) */
|
||||
#define VECTOR_NUMBER_SDHIMMC0_DMA_REQ ((IRQn_Type)30) /* SDHIMMC0 DMA REQ (DMA transfer request) */
|
||||
#define SDHIMMC0_DMA_REQ_IRQn ((IRQn_Type)30) /* SDHIMMC0 DMA REQ (DMA transfer request) */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* VECTOR_DATA_H */
|
||||
|
|
@ -0,0 +1,308 @@
|
|||
/*
|
||||
Linker File for RA6M5 MCU
|
||||
*/
|
||||
|
||||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1MB/2MB */
|
||||
FLASH_FS (r) : ORIGIN = 0x00100000, LENGTH = 0x00100000 /* 1MB/2MB */
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 /* 512KB */
|
||||
OSPI_RAM (rwx) : ORIGIN = 0x68000000, LENGTH = 0x00800000 /* 8MB/8MB */
|
||||
DATA_FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x00002000 /* 8KB */
|
||||
QSPI_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x01000000 /* 16MB/64MB */
|
||||
OSPI_FLASH (rx) : ORIGIN = 0x70000000, LENGTH = 0x01000000 /* 16MB/256MB */
|
||||
ID_CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000000 /* N/A */
|
||||
}
|
||||
|
||||
/* Library configurations */
|
||||
/*GROUP(libgcc.a libc.a libm.a libnosys.a) */
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_stext = .;
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
__end__ = .;
|
||||
|
||||
/* ROM Registers start at address 0x00000400 */
|
||||
. = __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = __ROM_Start + 0x500;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
_etext = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
_sidata = .;
|
||||
_sdata = .;
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
_estack = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
} > DATA_FLASH
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
}
|
||||
/* produce a link error if there is not this amount of RAM for these sections */
|
||||
/* _minimum_stack_size = 2K; */
|
||||
/* _minimum_heap_size = 16K; */
|
||||
|
||||
/* Define tho top end of the stack. The stack is full descending so begins just
|
||||
above last byte of RAM. Note that EABI requires the stack to be 8-byte
|
||||
aligned for a call. */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
/* RAM extents for the garbage collector */
|
||||
_ram_start = ORIGIN(RAM);
|
||||
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_heap_start = __HeapBase; /* heap starts just after statically allocated memory */
|
||||
_heap_end = __HeapLimit; /* tunable */
|
||||
|
||||
_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS);
|
||||
_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
|
||||
|
||||
_micropy_hw_external_flash_storage_start = ORIGIN(QSPI_FLASH);
|
||||
_micropy_hw_external_flash_storage_end = ORIGIN(QSPI_FLASH) + LENGTH(QSPI_FLASH);
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023 Vekatech Ltd.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef VK_RA6M5_CONF_H
|
||||
#define VK_RA6M5_CONF_H
|
||||
|
||||
#define DEBUG_CH 7
|
||||
|
||||
#endif /* VK_RA6M5_CONF_H */
|
||||
Loading…
Reference in New Issue