Merge pull request #112 from iabdalkader/master
Use LSI OSC for RTC clock when LSE is not detected
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commit
ea9e441a75
25
stm/main.c
25
stm/main.c
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@ -585,6 +585,9 @@ mp_obj_t pyb_hid_send_report(mp_obj_t arg) {
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}
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}
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static void rtc_init(void) {
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static void rtc_init(void) {
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uint32_t rtc_clksrc;
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uint32_t timeout =10000;
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/* Enable the PWR clock */
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/* Enable the PWR clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
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@ -595,11 +598,29 @@ static void rtc_init(void) {
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RCC_LSEConfig(RCC_LSE_ON);
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RCC_LSEConfig(RCC_LSE_ON);
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/* Wait till LSE is ready */
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/* Wait till LSE is ready */
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while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) {
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while((RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--timeout > 0)) {
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}
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/* If LSE timed out, use LSI instead */
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if (timeout == 0) {
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/* Enable the LSI OSC */
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RCC_LSICmd(ENABLE);
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/* Wait till LSI is ready */
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while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {
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}
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/* Use LSI as the RTC Clock Source */
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rtc_clksrc = RCC_RTCCLKSource_LSI;
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} else {
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/* Use LSE as the RTC Clock Source */
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rtc_clksrc = RCC_RTCCLKSource_LSE;
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}
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}
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/* Select the RTC Clock Source */
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/* Select the RTC Clock Source */
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RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
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RCC_RTCCLKConfig(rtc_clksrc);
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/* Note: LSI is around (32KHz), these dividers should work either way */
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/* ck_spre(1Hz) = RTCCLK(LSE) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)*/
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/* ck_spre(1Hz) = RTCCLK(LSE) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)*/
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uint32_t uwSynchPrediv = 0xFF;
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uint32_t uwSynchPrediv = 0xFF;
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uint32_t uwAsynchPrediv = 0x7F;
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uint32_t uwAsynchPrediv = 0x7F;
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