stm32/mboot: Add support for H7 MCUs, with H743 flash layout.
This commit is contained in:
Damien George
parent
ae1e18a346
commit
fd13ce5e60
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@ -48,6 +48,7 @@ CFLAGS_CORTEX_M = -mthumb
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# Options for particular MCU series
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CFLAGS_MCU_f4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
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CFLAGS_MCU_f7 = $(CFLAGS_CORTEX_M) -mtune=cortex-m7 -mcpu=cortex-m7
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CFLAGS_MCU_h7 = $(CFLAGS_CORTEX_M) -mtune=cortex-m7 -mcpu=cortex-m7
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CFLAGS_MCU_l4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
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CFLAGS = $(INC) -Wall -Wpointer-arith -Werror -std=gnu99 -nostdlib $(CFLAGS_MOD) $(CFLAGS_EXTRA)
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@ -3,7 +3,7 @@
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2017-2018 Damien P. George
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* Copyright (c) 2017-2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -38,7 +38,7 @@
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// This DFU code with polling runs in about 70% of the time of the ST bootloader
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#define USE_USB_POLLING (1)
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// Using cache probably won't make it faster because we run at 48MHz, and best
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// Using cache probably won't make it faster because we run at a low frequency, and best
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// to keep the MCU config as minimal as possible.
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#define USE_CACHE (0)
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@ -46,18 +46,25 @@
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#define IRQ_PRI_SYSTICK (NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 0, 0))
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#define IRQ_PRI_I2C (NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0))
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// Configure PLL to give a 48MHz CPU freq
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// Configure PLL to give the desired CPU freq
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#undef MICROPY_HW_FLASH_LATENCY
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#if defined(STM32H7)
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#define CORE_PLL_FREQ (96000000)
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#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_2
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#else
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#define CORE_PLL_FREQ (48000000)
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#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_1
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#endif
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#undef MICROPY_HW_CLK_PLLM
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#undef MICROPY_HW_CLK_PLLN
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#undef MICROPY_HW_CLK_PLLP
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#undef MICROPY_HW_CLK_PLLQ
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#undef MICROPY_HW_FLASH_LATENCY
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#undef MICROPY_HW_CLK_PLLR
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#define MICROPY_HW_CLK_PLLM (HSE_VALUE / 1000000)
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#define MICROPY_HW_CLK_PLLN (192)
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#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV4)
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#define MICROPY_HW_CLK_PLLP (MICROPY_HW_CLK_PLLN / (CORE_PLL_FREQ / 1000000))
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#define MICROPY_HW_CLK_PLLQ (4)
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#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_1
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#define MICROPY_HW_CLK_PLLR (2)
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// Work out which USB device to use for the USB DFU interface
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#if !defined(MICROPY_HW_USB_MAIN_DEV)
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@ -137,11 +144,25 @@ static void __fatal_error(const char *msg) {
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#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON || RCC_CR_CSSON || RCC_CR_PLLON)
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#define CONFIG_RCC_PLLCFGR (0x24003010)
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#elif defined(STM32H7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (RCC_CR_PLL3ON | RCC_CR_PLL2ON | RCC_CR_PLL1ON | RCC_CR_CSSHSEON \
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| RCC_CR_HSEON | RCC_CR_HSI48ON | RCC_CR_CSIKERON | RCC_CR_CSION)
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#define CONFIG_RCC_PLLCFGR (0x00000000)
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#else
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#error Unknown processor
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#endif
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void SystemInit(void) {
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#if defined(STM32H7)
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// Configure write-once power options, and wait for voltage levels to be ready
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PWR->CR3 = PWR_CR3_LDOEN;
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while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY)) {
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}
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#endif
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// Set HSION bit
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RCC->CR |= CONFIG_RCC_CR_1ST;
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@ -154,11 +175,27 @@ void SystemInit(void) {
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// Reset PLLCFGR register
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(STM32H7)
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// Reset PLL and clock configuration registers
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RCC->D1CFGR = 0x00000000;
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RCC->D2CFGR = 0x00000000;
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RCC->D3CFGR = 0x00000000;
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RCC->PLLCKSELR = 0x00000000;
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RCC->D1CCIPR = 0x00000000;
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RCC->D2CCIP1R = 0x00000000;
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RCC->D2CCIP2R = 0x00000000;
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RCC->D3CCIPR = 0x00000000;
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#endif
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// Reset HSEBYP bit
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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// Disable all interrupts
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#if defined(STM32F4) || defined(STM32F7)
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RCC->CIR = 0x00000000;
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#elif defined(STM32H7)
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RCC->CIER = 0x00000000;
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#endif
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// Set location of vector table
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SCB->VTOR = FLASH_BASE;
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@ -173,6 +210,8 @@ void systick_init(void) {
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NVIC_SetPriority(SysTick_IRQn, IRQ_PRI_SYSTICK);
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}
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#if defined(STM32F4) || defined(STM32F7)
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void SystemClock_Config(void) {
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// This function assumes that HSI is used as the system clock (see RCC->CFGR, SWS bits)
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@ -243,6 +282,87 @@ void SystemClock_Config(void) {
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#endif
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}
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#elif defined(STM32H7)
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void SystemClock_Config(void) {
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// This function assumes that HSI is used as the system clock (see RCC->CFGR, SWS bits)
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// Select VOS level as high voltage to give reliable operation
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET) {
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}
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// Turn HSE on
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__HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) {
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}
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// Disable PLL1
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__HAL_RCC_PLL_DISABLE();
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while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) {
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}
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// Configure PLL1 factors and source
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RCC->PLLCKSELR =
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MICROPY_HW_CLK_PLLM << RCC_PLLCKSELR_DIVM1_Pos
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| 2 << RCC_PLLCKSELR_PLLSRC_Pos; // HSE selected as PLL source
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RCC->PLL1DIVR =
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(MICROPY_HW_CLK_PLLN - 1) << RCC_PLL1DIVR_N1_Pos
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| (MICROPY_HW_CLK_PLLP - 1) << RCC_PLL1DIVR_P1_Pos // only even P allowed
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| (MICROPY_HW_CLK_PLLQ - 1) << RCC_PLL1DIVR_Q1_Pos
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| (MICROPY_HW_CLK_PLLR - 1) << RCC_PLL1DIVR_R1_Pos;
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// Enable PLL1 outputs for SYSCLK and USB
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RCC->PLLCFGR = RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN;
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// Select PLL1-Q for USB clock source
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RCC->D2CCIP2R |= 1 << RCC_D2CCIP2R_USBSEL_Pos;
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// Enable PLL1
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__HAL_RCC_PLL_ENABLE();
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
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}
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// Increase latency before changing SYSCLK
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if (MICROPY_HW_FLASH_LATENCY > (FLASH->ACR & FLASH_ACR_LATENCY)) {
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__HAL_FLASH_SET_LATENCY(MICROPY_HW_FLASH_LATENCY);
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}
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// Configure AHB divider
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RCC->D1CFGR =
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0 << RCC_D1CFGR_D1CPRE_Pos // SYSCLK prescaler of 1
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| 8 << RCC_D1CFGR_HPRE_Pos // AHB prescaler of 2
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;
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// Configure SYSCLK source from PLL
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__HAL_RCC_SYSCLK_CONFIG(RCC_SYSCLKSOURCE_PLLCLK);
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while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) {
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}
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// Decrease latency after changing clock
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if (MICROPY_HW_FLASH_LATENCY < (FLASH->ACR & FLASH_ACR_LATENCY)) {
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__HAL_FLASH_SET_LATENCY(MICROPY_HW_FLASH_LATENCY);
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}
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// Set APB clock dividers
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RCC->D1CFGR |=
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4 << RCC_D1CFGR_D1PPRE_Pos // APB3 prescaler of 2
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;
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RCC->D2CFGR =
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4 << RCC_D2CFGR_D2PPRE2_Pos // APB2 prescaler of 2
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| 4 << RCC_D2CFGR_D2PPRE1_Pos // APB1 prescaler of 2
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;
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RCC->D3CFGR =
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4 << RCC_D3CFGR_D3PPRE_Pos // APB4 prescaler of 2
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;
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// Update clock value and reconfigure systick now that the frequency changed
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SystemCoreClock = CORE_PLL_FREQ;
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systick_init();
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}
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#endif
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// Needed by HAL_PCD_IRQHandler
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uint32_t HAL_RCC_GetHCLKFreq(void) {
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return SystemCoreClock;
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@ -251,13 +371,21 @@ uint32_t HAL_RCC_GetHCLKFreq(void) {
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/******************************************************************************/
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// GPIO
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#if defined(STM32F4) || defined(STM32F7)
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#define AHBxENR AHB1ENR
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#define AHBxENR_GPIOAEN_Pos RCC_AHB1ENR_GPIOAEN_Pos
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#elif defined(STM32H7)
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#define AHBxENR AHB4ENR
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#define AHBxENR_GPIOAEN_Pos RCC_AHB4ENR_GPIOAEN_Pos
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#endif
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void mp_hal_pin_config(mp_hal_pin_obj_t port_pin, uint32_t mode, uint32_t pull, uint32_t alt) {
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GPIO_TypeDef *gpio = (GPIO_TypeDef*)(port_pin & ~0xf);
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// Enable the GPIO peripheral clock
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uint32_t en_bit = RCC_AHB1ENR_GPIOAEN_Pos + ((uintptr_t)gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
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RCC->AHB1ENR |= 1 << en_bit;
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volatile uint32_t tmp = RCC->AHB1ENR; // Delay after enabling clock
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uint32_t gpio_idx = ((uintptr_t)gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
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RCC->AHBxENR |= 1 << (AHBxENR_GPIOAEN_Pos + gpio_idx);
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volatile uint32_t tmp = RCC->AHBxENR; // Delay after enabling clock
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(void)tmp;
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// Configure the pin
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@ -381,6 +509,14 @@ static const flash_layout_t flash_layout[] = {
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{ 0x08040000, 0x40000, 7 },
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};
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#elif defined(STM32H743xx)
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#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/16*128Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT
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static const flash_layout_t flash_layout[] = {
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{ 0x08000000, 0x20000, 16 },
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};
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#endif
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static uint32_t flash_get_sector_index(uint32_t addr, uint32_t *sector_size) {
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@ -401,6 +537,27 @@ static uint32_t flash_get_sector_index(uint32_t addr, uint32_t *sector_size) {
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return 0;
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}
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#if defined(STM32H7)
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// get the bank of a given flash address
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static uint32_t get_bank(uint32_t addr) {
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if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == 0) {
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// no bank swap
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if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
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return FLASH_BANK_1;
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} else {
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return FLASH_BANK_2;
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}
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} else {
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// bank swap
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if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
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return FLASH_BANK_2;
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} else {
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return FLASH_BANK_1;
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}
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}
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}
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#endif
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static int flash_mass_erase(void) {
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// TODO
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return -1;
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@ -419,13 +576,20 @@ static int flash_page_erase(uint32_t addr, uint32_t *next_addr) {
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HAL_FLASH_Unlock();
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// Clear pending flags (if any)
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#if defined(STM32H7)
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2);
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#else
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
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FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
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#endif
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// erase the sector(s)
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FLASH_EraseInitTypeDef EraseInitStruct;
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EraseInitStruct.TypeErase = TYPEERASE_SECTORS;
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EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V
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#if defined(STM32H7)
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EraseInitStruct.Banks = get_bank(addr);
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#endif
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EraseInitStruct.Sector = sector;
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EraseInitStruct.NbSectors = 1;
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@ -454,6 +618,20 @@ static int flash_write(uint32_t addr, const uint8_t *src8, size_t len) {
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const uint32_t *src = (const uint32_t*)src8;
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size_t num_word32 = (len + 3) / 4;
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HAL_FLASH_Unlock();
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#if defined(STM32H7)
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// program the flash 256 bits at a time
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for (int i = 0; i < num_word32 / 8; ++i) {
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if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, addr, (uint64_t)(uint32_t)src) != HAL_OK) {
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return - 1;
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}
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addr += 32;
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src += 8;
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}
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#else
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// program the flash word by word
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for (size_t i = 0; i < num_word32; i++) {
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if (HAL_FLASH_Program(TYPEPROGRAM_WORD, addr, *src) != HAL_OK) {
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@ -463,6 +641,8 @@ static int flash_write(uint32_t addr, const uint8_t *src8, size_t len) {
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src += 1;
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}
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#endif
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// TODO verify data
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return 0;
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@ -1130,6 +1310,11 @@ static void pyb_usbdd_init(pyb_usbdd_obj_t *self, int phy_id) {
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static void pyb_usbdd_start(pyb_usbdd_obj_t *self) {
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if (!self->started) {
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#if defined(STM32H7)
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PWR->CR3 |= PWR_CR3_USB33DEN;
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while (!(PWR->CR3 & PWR_CR3_USB33RDY)) {
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}
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#endif
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USBD_LL_Init(&self->hUSBDDevice, 0);
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USBD_LL_Start(&self->hUSBDDevice);
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self->started = true;
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@ -1249,8 +1434,8 @@ void stm32_main(int initial_r0) {
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goto enter_bootloader;
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}
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// MCU starts up with 16MHz HSI
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SystemCoreClock = 16000000;
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// MCU starts up with HSI
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SystemCoreClock = HSI_VALUE;
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int reset_mode = get_reset_mode();
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uint32_t msp = *(volatile uint32_t*)APPLICATION_ADDR;
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@ -48,8 +48,13 @@
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#define mp_hal_pin_input(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_INPUT, MP_HAL_PIN_PULL_NONE, 0)
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#define mp_hal_pin_output(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_OUTPUT, MP_HAL_PIN_PULL_NONE, 0)
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#define mp_hal_pin_open_drain(p) mp_hal_pin_config((p), MP_HAL_PIN_MODE_OPEN_DRAIN, MP_HAL_PIN_PULL_NONE, 0)
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#if defined(STM32H7)
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#define mp_hal_pin_low(p) (((GPIO_TypeDef*)((p) & ~0xf))->BSRRH = 1 << ((p) & 0xf))
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#define mp_hal_pin_high(p) (((GPIO_TypeDef*)((p) & ~0xf))->BSRRL = 1 << ((p) & 0xf))
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#else
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#define mp_hal_pin_low(p) (((GPIO_TypeDef*)((p) & ~0xf))->BSRR = 0x10000 << ((p) & 0xf))
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#define mp_hal_pin_high(p) (((GPIO_TypeDef*)((p) & ~0xf))->BSRR = 1 << ((p) & 0xf))
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#endif
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#define mp_hal_pin_od_low(p) mp_hal_pin_low(p)
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#define mp_hal_pin_od_high(p) mp_hal_pin_high(p)
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#define mp_hal_pin_read(p) ((((GPIO_TypeDef*)((p) & ~0xf))->IDR >> ((p) & 0xf)) & 1)
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