For SAMD21 devices, the board flash signals must be named in pins.csv as
FLASH_MOSI, FLASH_MISO, FLASH_SCK, FLASH_CS for creating the SPI object.
And rename the QSPI pins to QSPI_xxxx instead of FLASH_xxx.
Signed-off-by: robert-hh <robert@hammelrath.com>
By specifying rts=pin(x) and/or cts=Pin(x) in the constructor. The pad
numbers for the UART pins are fix in this case: TX must be at pad 0, RX at
pad 1, RTS at pad 2 and CTS at pad 3.
repr(uart) shows the pin names for rts and cts, if set. In case of a RX
overflow, the rx interrupt will be disabled instead of just discarding the
data. That allows RTS to act.
If RTS is inactive, still 2 bytes can be buffered in the FIFO.
Signed-off-by: robert-hh <robert@hammelrath.com>
This adds the freq and duty_u16 keyword settings to the constructor, and
sometimes other details in the PWM section.
For mimxrt a clarification regarding the PWM invert argument was added, and
for rp2 a few words were spent on PWM output pairs of a channel/slice.
The PWM.init() method has been added. Calling init() without arguments
restarts a PWM channel stopped with deinit(). Otherwise single parameters
except for "device=n" can be changed again. The device can only be
specified once, either in the constructor or the first init() call.
Also simplify get_pwm_config() and get_adc_config(), and shrink the PWM
object.
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock.
Even if both use the same reference source, they have a different jitter.
SysTick is driven by FDPLL96M, the us counter by DFLL48M. As a random
source, the us counter is read out on every SysTick and the value is used
to accumulate a simple multiply, add and xor register. According to tests
it creates about 30 bit random bit-flips per second. That mechanism will
pass quite a few RNG tests, has a suitable frequency distribution and
serves better than just the time after boot to seed the PRNG.
ADC: The argument of vref=num is an integer. Values for num are:
SAMD21:
0 INT1V 1.0V voltage reference
1 INTVCC0 1/1.48 Analog voltage supply
2 INTVCC1 1/2 Analog voltage supply (only for VDDANA > 2.0V)
3 VREFA External reference
4 VREFB External reference
SAMD51:
0 INTREF internal bandgap reference
1 INTVCC1 Analog voltage supply
2 INTVCC0 1/2 Analog voltage supply (only for VDDANA > 2.0v)
3 AREFA External reference A
4 AREFB External reference B
5 AREFC External reference C (ADC1 only)
DAC: The argument of vref=num is an integer. Suitable values:
SAMD21:
0 INT1V Internal voltage reference
1 VDDANA Analog voltage supply
2 VREFA External reference
SAMD51:
0 INTREF Internal bandgap reference
1 VDDANA Analog voltage supply
2 VREFAU Unbuffered external voltage reference (not buffered in DAC)
4 VREFAB Buffered external voltage reference (buffered in DAC).
robert-hh