This RNG passes many of the Diehard tests and also the AIS31 test suite.
The RNG is quite slow, delivering 200bytes/s.
Tested on boards with and without a crystal.
By using the phase jitter between the DFLL48M clock and the FDPLL96M clock.
Even if both use the same reference source, they have a different jitter.
SysTick is driven by FDPLL96M, the us counter by DFLL48M. As a random
source, the us counter is read out on every SysTick and the value is used
to accumulate a simple multiply, add and xor register. According to tests
it creates about 30 bit random bit-flips per second. That mechanism will
pass quite a few RNG tests, has a suitable frequency distribution and
serves better than just the time after boot to seed the PRNG.
This removes the difference in the time.ticks_us() range between SAMD21 and
SAMD51.
The function mp_hal_ticks_us_64() is added and used for:
- SAMD51's mp_hal_ticks_us and mp_hal_delay_us().
For SAMD21, keep the previous methods, which are faster.
- mp_hal_ticks_ms() and mp_hal_tick_ms_64(), which saves some bytes
and removes a potential race condition every 50 days.
Also set the us-counter for SAMD51 to 16 MHz for a faster reading of the
microsecond value.
Note: With SAMD51, mp_hal_ticks_us_64() has a 60 bit range only, which is
still a long time (~36000 years).
All board pins that have UART's assigned can be used. Baud rate range is
75 Baud to ~2 MBaud.
No flow control yet, and only RX is buffered. TX buffer and flow control
may be added later for SAMD51 with its larger RAM and Flash.
Its API conforms to the docs. There are 16 IRQ channels available, which
will be used as assignable to the GPIO numbers. In most cases, the irq
channel is GPIO_no % 16.
Changes are:
- Have two separate tables for SAM21 and SAMD51.
- Use a short table for SAMD21.
- Add a comment to each line telling what it's for, making further use
easier.
- Add preliminary handlers/entries for PendSV, EIC and Sercom. These will
be replaced later when the respecitve modules are added.
robert-hh
Damien George