426 lines
17 KiB
C
426 lines
17 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "mpu.h"
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#include "qspi.h"
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#include "pin_static_af.h"
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#if defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2)
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#define QSPI_MAP_ADDR (0x90000000)
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#ifndef MICROPY_HW_QSPI_PRESCALER
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#define MICROPY_HW_QSPI_PRESCALER 3 // F_CLK = F_AHB/3 (72MHz when CPU is 216MHz)
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#endif
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#ifndef MICROPY_HW_QSPI_SAMPLE_SHIFT
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#define MICROPY_HW_QSPI_SAMPLE_SHIFT 1 // sample shift enabled
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#endif
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#ifndef MICROPY_HW_QSPI_TIMEOUT_COUNTER
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#define MICROPY_HW_QSPI_TIMEOUT_COUNTER 0 // timeout counter disabled (see F7 errata)
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#endif
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#ifndef MICROPY_HW_QSPI_CS_HIGH_CYCLES
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#define MICROPY_HW_QSPI_CS_HIGH_CYCLES 2 // nCS stays high for 2 cycles
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#endif
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#ifndef MICROPY_HW_QSPI_MPU_REGION_SIZE
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#define MICROPY_HW_QSPI_MPU_REGION_SIZE ((1 << (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3)) >> 20)
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#endif
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#if (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) >= 24
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#define QSPI_CMD 0xec
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#define QSPI_ADSIZE 3
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#else
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#define QSPI_CMD 0xeb
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#define QSPI_ADSIZE 2
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#endif
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static inline void qspi_mpu_disable_all(void) {
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// Configure MPU to disable access to entire QSPI region, to prevent CPU
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// speculative execution from accessing this region and modifying QSPI registers.
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uint32_t irq_state = mpu_config_start();
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x00, MPU_REGION_SIZE_256MB));
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mpu_config_end(irq_state);
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}
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static inline void qspi_mpu_enable_mapped(void) {
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// Configure MPU to allow access to only the valid part of external SPI flash.
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// The memory accesses to the mapped QSPI are faster if the MPU is not used
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// for the memory-mapped region, so 3 MPU regions are used to disable access
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// to everything except the valid address space, using holes in the bottom
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// of the regions and nesting them.
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// Note: Disabling a subregion (by setting its corresponding SRD bit to 1)
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// means another region overlapping the disabled range matches instead. If no
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// other enabled region overlaps the disabled subregion, and the access is
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// unprivileged or the background region is disabled, the MPU issues a fault.
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uint32_t irq_state = mpu_config_start();
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#if MICROPY_HW_QSPI_MPU_REGION_SIZE > 128
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0xFF, MPU_REGION_SIZE_256MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 64
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_256MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 32
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_256MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 16
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 8
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
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mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_32MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 4
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
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mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_32MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 2
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
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mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_32MB));
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#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 1
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
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mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_32MB));
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mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_16MB));
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#else
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mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB));
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mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_32MB));
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mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_4MB));
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#endif
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mpu_config_end(irq_state);
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}
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void qspi_init(void) {
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qspi_mpu_disable_all();
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// Configure pins
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_QSPIFLASH_CS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_QUADSPI_BK1_NCS);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_QSPIFLASH_SCK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_QUADSPI_CLK);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_QSPIFLASH_IO0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_QUADSPI_BK1_IO0);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_QSPIFLASH_IO1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_QUADSPI_BK1_IO1);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_QSPIFLASH_IO2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_QUADSPI_BK1_IO2);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_QSPIFLASH_IO3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_QUADSPI_BK1_IO3);
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// Bring up the QSPI peripheral
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__HAL_RCC_QSPI_CLK_ENABLE();
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__HAL_RCC_QSPI_FORCE_RESET();
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__HAL_RCC_QSPI_RELEASE_RESET();
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QUADSPI->CR =
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(MICROPY_HW_QSPI_PRESCALER - 1) << QUADSPI_CR_PRESCALER_Pos
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| 3 << QUADSPI_CR_FTHRES_Pos // 4 bytes must be available to read/write
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#if defined(QUADSPI_CR_FSEL_Pos)
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| 0 << QUADSPI_CR_FSEL_Pos // FLASH 1 selected
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#endif
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#if defined(QUADSPI_CR_DFM_Pos)
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| 0 << QUADSPI_CR_DFM_Pos // dual-flash mode disabled
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#endif
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| MICROPY_HW_QSPI_SAMPLE_SHIFT << QUADSPI_CR_SSHIFT_Pos
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| MICROPY_HW_QSPI_TIMEOUT_COUNTER << QUADSPI_CR_TCEN_Pos
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| 1 << QUADSPI_CR_EN_Pos // enable the peripheral
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;
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QUADSPI->DCR =
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(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) << QUADSPI_DCR_FSIZE_Pos
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| (MICROPY_HW_QSPI_CS_HIGH_CYCLES - 1) << QUADSPI_DCR_CSHT_Pos
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| 0 << QUADSPI_DCR_CKMODE_Pos // CLK idles at low state
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;
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}
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void qspi_memory_map(void) {
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// Enable memory-mapped mode
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QUADSPI->ABR = 0; // disable continuous read mode
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 3 << QUADSPI_CCR_FMODE_Pos // memory-mapped mode
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| 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines
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| 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles
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| 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
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| 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines
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| QSPI_ADSIZE << QUADSPI_CCR_ADSIZE_Pos
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| 3 << QUADSPI_CCR_ADMODE_Pos // address on 4 lines
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| QSPI_CMD << QUADSPI_CCR_INSTRUCTION_Pos
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;
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qspi_mpu_enable_mapped();
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}
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STATIC int qspi_ioctl(void *self_in, uint32_t cmd) {
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(void)self_in;
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switch (cmd) {
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case MP_QSPI_IOCTL_INIT:
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qspi_init();
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break;
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case MP_QSPI_IOCTL_BUS_ACQUIRE:
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// Disable memory-mapped region during bus access
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qspi_mpu_disable_all();
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// Abort any ongoing transfer if peripheral is busy
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if (QUADSPI->SR & QUADSPI_SR_BUSY) {
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QUADSPI->CR |= QUADSPI_CR_ABORT;
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while (QUADSPI->CR & QUADSPI_CR_ABORT) {
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}
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}
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break;
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case MP_QSPI_IOCTL_BUS_RELEASE:
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// Switch to memory-map mode when bus is idle
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qspi_memory_map();
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break;
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}
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return 0; // success
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}
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STATIC int qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t data) {
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(void)self_in;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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if (len == 0) {
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 0 << QUADSPI_CCR_DMODE_Pos // no data
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << QUADSPI_CCR_ADMODE_Pos // no address
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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} else {
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QUADSPI->DLR = len - 1;
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 1 << QUADSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << QUADSPI_CCR_ADMODE_Pos // no address
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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// Wait for at least 1 free byte location in the FIFO.
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while (!(QUADSPI->SR & QUADSPI_SR_FTF)) {
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}
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if (len == 1) {
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*(uint8_t *)&QUADSPI->DR = data;
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} else {
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// This assumes len==2
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*(uint16_t *)&QUADSPI->DR = data;
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}
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}
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// Wait for write to finish
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while (!(QUADSPI->SR & QUADSPI_SR_TCF)) {
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if (QUADSPI->SR & QUADSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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return 0;
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}
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STATIC int qspi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
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(void)self_in;
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uint8_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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if (len == 0) {
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 0 << QUADSPI_CCR_DMODE_Pos // no data
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| adsize << QUADSPI_CCR_ADSIZE_Pos // 32/24-bit address size
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| 1 << QUADSPI_CCR_ADMODE_Pos // address on 1 line
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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QUADSPI->AR = addr;
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} else {
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QUADSPI->DLR = len - 1;
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_FMODE_Pos // indirect write mode
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| 1 << QUADSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| adsize << QUADSPI_CCR_ADSIZE_Pos // 32/24-bit address size
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| 1 << QUADSPI_CCR_ADMODE_Pos // address on 1 line
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // write opcode
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;
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QUADSPI->AR = addr;
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// Write out the data 1 byte at a time
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while (len) {
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while (!(QUADSPI->SR & QUADSPI_SR_FTF)) {
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if (QUADSPI->SR & QUADSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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*(volatile uint8_t *)&QUADSPI->DR = *src++;
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--len;
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}
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}
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// Wait for write to finish
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while (!(QUADSPI->SR & QUADSPI_SR_TCF)) {
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if (QUADSPI->SR & QUADSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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return 0;
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}
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STATIC int qspi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_t *dest) {
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(void)self_in;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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QUADSPI->DLR = len - 1; // number of bytes to read
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode
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| 1 << QUADSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << QUADSPI_CCR_DCYC_Pos // 0 dummy cycles
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| 0 << QUADSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << QUADSPI_CCR_ADMODE_Pos // no address
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // read opcode
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;
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// Wait for read to finish
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while (!(QUADSPI->SR & QUADSPI_SR_TCF)) {
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if (QUADSPI->SR & QUADSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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// Read result
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*dest = QUADSPI->DR;
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return 0;
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}
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STATIC int qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
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(void)self_in;
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uint8_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2;
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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QUADSPI->DLR = len - 1; // number of bytes to read
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QUADSPI->CCR =
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode
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| 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines
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| 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles
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| 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
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| 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines
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| adsize << QUADSPI_CCR_ADSIZE_Pos // 32 or 24-bit address size
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| 3 << QUADSPI_CCR_ADMODE_Pos // address on 4 lines
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // quad read opcode
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;
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QUADSPI->ABR = 0; // alternate byte: disable continuous read mode
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QUADSPI->AR = addr; // address to read from
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#if defined(STM32H7)
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// Workaround for SR getting set immediately after setting the address.
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if (QUADSPI->SR & 0x01) {
|
|
QUADSPI->FCR |= QUADSPI_FCR_CTEF;
|
|
QUADSPI->AR = addr; // address to read from
|
|
}
|
|
#endif
|
|
|
|
// Read in the data 4 bytes at a time if dest is aligned
|
|
if (((uintptr_t)dest & 3) == 0) {
|
|
while (len >= 4) {
|
|
while (!(QUADSPI->SR & QUADSPI_SR_FTF)) {
|
|
if (QUADSPI->SR & QUADSPI_SR_TEF) {
|
|
return -MP_EIO;
|
|
}
|
|
}
|
|
*(uint32_t *)dest = QUADSPI->DR;
|
|
dest += 4;
|
|
len -= 4;
|
|
}
|
|
}
|
|
|
|
// Read in remaining data 1 byte at a time
|
|
while (len) {
|
|
while (!((QUADSPI->SR >> QUADSPI_SR_FLEVEL_Pos) & 0x3f)) {
|
|
if (QUADSPI->SR & QUADSPI_SR_TEF) {
|
|
return -MP_EIO;
|
|
}
|
|
}
|
|
*dest++ = *(volatile uint8_t *)&QUADSPI->DR;
|
|
--len;
|
|
}
|
|
|
|
QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
|
|
|
|
return 0;
|
|
}
|
|
|
|
const mp_qspi_proto_t qspi_proto = {
|
|
.ioctl = qspi_ioctl,
|
|
.write_cmd_data = qspi_write_cmd_data,
|
|
.write_cmd_addr_data = qspi_write_cmd_addr_data,
|
|
.read_cmd = qspi_read_cmd,
|
|
.read_cmd_qaddr_qdata = qspi_read_cmd_qaddr_qdata,
|
|
};
|
|
|
|
#endif // defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2)
|