0941a467e7
The flash-IRQ handler is used to flush the storage cache, ie write outstanding block data from RAM to flash. This is triggered by a timeout, or by a direct call to flush all storage caches. Prior to this commit, a timeout could trigger the cache flushing to occur during the execution of a read/write to external SPI flash storage. In such a case the storage subsystem would break down. SPI storage transfers are already protected against USB IRQs, so by changing the priority of the flash IRQ to that of the USB IRQ (what is done in this commit) the SPI transfers can be protected against any timeouts triggering a cache flush (the cache flush would be postponed until after the transfer finished, but note that in the case of SPI writes the timeout is rescheduled after the transfer finishes). The handling of internal flash sync'ing needs to be changed to directly call flash_bdev_irq_handler() sync may be called with the IRQ priority already raised (eg when called from a USB MSC IRQ handler). |
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| bare-arm | ||
| cc3200 | ||
| esp32 | ||
| esp8266 | ||
| minimal | ||
| nrf | ||
| pic16bit | ||
| qemu-arm | ||
| stm32 | ||
| teensy | ||
| unix | ||
| windows | ||
| zephyr | ||