1049 lines
43 KiB
C
1049 lines
43 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_ll_fsmc.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 19-June-2014
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* @brief Header file of FSMC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_LL_FSMC_H
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#define __STM32F4xx_LL_FSMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup FSMC
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* @{
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*/
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/* Exported typedef ----------------------------------------------------------*/
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#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
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#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
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#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
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#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
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#define FSMC_NORSRAM_DEVICE FSMC_Bank1
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#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
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#define FSMC_NAND_DEVICE FSMC_Bank2_3
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#define FSMC_PCCARD_DEVICE FSMC_Bank4
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/**
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* @brief FSMC_NORSRAM Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
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This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
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multiplexed on the data bus or not.
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This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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uint32_t MemoryType; /*!< Specifies the type of external memory attached to
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the corresponding memory device.
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This parameter can be a value of @ref FSMC_Memory_Type */
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uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
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uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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valid only with synchronous burst Flash memories.
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This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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the Flash memory in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
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memory, valid only when accessing Flash memories in burst mode.
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This parameter can be a value of @ref FSMC_Wrap_Mode */
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uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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clock cycle before the wait state or during the wait state,
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valid only when accessing memories in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Timing */
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uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
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This parameter can be a value of @ref FSMC_Write_Operation */
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uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
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signal, valid for Flash memory access in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal */
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uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
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This parameter can be a value of @ref FSMC_Extended_Mode */
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uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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valid only with asynchronous Flash memories.
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This parameter can be a value of @ref FSMC_AsynchronousWait */
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uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
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This parameter can be a value of @ref FSMC_Write_Burst */
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}FSMC_NORSRAM_InitTypeDef;
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/**
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* @brief FSMC_NORSRAM Timing parameters structure definition
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*/
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typedef struct
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{
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uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address setup time.
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This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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@note This parameter is not used with synchronous NOR Flash memories. */
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uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address hold time.
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This parameter can be a value between Min_Data = 1 and Max_Data = 15.
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@note This parameter is not used with synchronous NOR Flash memories. */
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uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the data setup time.
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This parameter can be a value between Min_Data = 1 and Max_Data = 255.
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@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
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NOR Flash memories. */
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uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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the duration of the bus turnaround.
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This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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@note This parameter is only used for multiplexed NOR Flash memories. */
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uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
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HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
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@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
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accesses. */
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uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
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to the memory before getting the first data.
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The parameter value depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
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with synchronous burst mode enable */
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uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
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This parameter can be a value of @ref FSMC_Access_Mode */
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}FSMC_NORSRAM_TimingTypeDef;
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/**
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* @brief FSMC_NAND Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
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This parameter can be a value of @ref FSMC_NAND_Bank */
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uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
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This parameter can be any value of @ref FSMC_Wait_feature */
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uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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This parameter can be any value of @ref FSMC_NAND_Data_Width */
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uint32_t EccComputation; /*!< Enables or disables the ECC computation.
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This parameter can be any value of @ref FSMC_ECC */
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uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
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This parameter can be any value of @ref FSMC_ECC_Page_Size */
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uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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}FSMC_NAND_InitTypeDef;
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/**
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* @brief FSMC_NAND_PCCARD Timing parameters structure definition
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*/
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typedef struct
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{
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uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
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the command assertion for NAND-Flash read or write access
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to common/Attribute or I/O memory space (depending on
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the memory space timing to be configured).
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
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command for NAND-Flash read or write access to
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common/Attribute or I/O memory space (depending on the
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memory space timing to be configured).
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
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(and data for write access) after the command de-assertion
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for NAND-Flash read or write access to common/Attribute
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or I/O memory space (depending on the memory space timing
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to be configured).
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
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data bus is kept in HiZ after the start of a NAND-Flash
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write access to common/Attribute or I/O memory space (depending
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on the memory space timing to be configured).
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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}FSMC_NAND_PCC_TimingTypeDef;
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/**
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* @brief FSMC_NAND Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
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This parameter can be any value of @ref FSMC_Wait_feature */
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uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
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}FSMC_PCCARD_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup FSMC_NOR_SRAM_Controller
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* @{
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*/
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/** @defgroup FSMC_NORSRAM_Bank
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* @{
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*/
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#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
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#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
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#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
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#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
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#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
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((BANK) == FSMC_NORSRAM_BANK2) || \
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((BANK) == FSMC_NORSRAM_BANK3) || \
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((BANK) == FSMC_NORSRAM_BANK4))
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/**
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* @}
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*/
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/** @defgroup FSMC_Data_Address_Bus_Multiplexing
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* @{
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*/
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#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
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#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
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#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
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((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Memory_Type
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* @{
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*/
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#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
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#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
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#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
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#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
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((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
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((MEMORY) == FSMC_MEMORY_TYPE_NOR))
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/**
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* @}
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*/
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/** @defgroup FSMC_NORSRAM_Data_Width
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* @{
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*/
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#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
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#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
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#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
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#define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
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((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
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((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
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/**
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* @}
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*/
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/** @defgroup FSMC_NORSRAM_Flash_Access
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* @{
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*/
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#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
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#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup FSMC_Burst_Access_Mode
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* @{
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*/
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#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
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#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
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#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
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((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Signal_Polarity
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* @{
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*/
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#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
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#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
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#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
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((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wrap_Mode
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* @{
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*/
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#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
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#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
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#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
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((MODE) == FSMC_WRAP_MODE_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Timing
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* @{
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*/
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#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
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#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
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#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
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((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
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/**
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* @}
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*/
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/** @defgroup FSMC_Write_Operation
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* @{
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*/
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#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
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#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
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#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
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((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Wait_Signal
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* @{
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*/
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#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
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#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
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#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
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((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Extended_Mode
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* @{
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*/
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#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
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#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
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#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
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((MODE) == FSMC_EXTENDED_MODE_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_AsynchronousWait
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* @{
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*/
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#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
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#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
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#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
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((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Write_Burst
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* @{
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*/
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#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
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#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
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#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
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((BURST) == FSMC_WRITE_BURST_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FSMC_Continous_Clock
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* @{
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*/
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#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
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#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
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#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
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((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
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/**
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* @}
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*/
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/** @defgroup FSMC_Address_Setup_Time
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* @{
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*/
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#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
|
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/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Address_Hold_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Data_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Bus_Turn_around_Duration
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_CLK_Division
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Data_Latency
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Access_Mode
|
|
* @{
|
|
*/
|
|
#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
|
|
#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
|
|
#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
|
|
#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
|
|
|
|
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
|
|
((MODE) == FSMC_ACCESS_MODE_B) || \
|
|
((MODE) == FSMC_ACCESS_MODE_C) || \
|
|
((MODE) == FSMC_ACCESS_MODE_D))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NAND_Controller
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup FSMC_NAND_Bank
|
|
* @{
|
|
*/
|
|
#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
|
|
#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
|
|
|
|
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
|
|
((BANK) == FSMC_NAND_BANK3))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Wait_feature
|
|
* @{
|
|
*/
|
|
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
|
|
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
|
|
|
|
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
|
|
((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_PCR_Memory_Type
|
|
* @{
|
|
*/
|
|
#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
|
|
#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NAND_Data_Width
|
|
* @{
|
|
*/
|
|
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
|
|
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
|
|
|
|
#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
|
|
((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_ECC
|
|
* @{
|
|
*/
|
|
#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
|
|
#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
|
|
|
|
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
|
|
((STATE) == FSMC_NAND_ECC_ENABLE))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_ECC_Page_Size
|
|
* @{
|
|
*/
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
|
|
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
|
|
|
|
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
|
|
((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
|
|
((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
|
|
((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
|
|
((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
|
|
((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_TCLR_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_TAR_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Wait_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Hold_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_HiZ_Setup_Time
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup FSMC_NORSRAM_Device_Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_NAND_Device_Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_PCCARD_Device_Instance
|
|
* @{
|
|
*/
|
|
#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Interrupt_definition
|
|
* @brief FSMC Interrupt definition
|
|
* @{
|
|
*/
|
|
#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
|
|
#define FSMC_IT_LEVEL ((uint32_t)0x00000010)
|
|
#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
|
|
#define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
|
|
|
|
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
|
|
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
|
|
((IT) == FSMC_IT_LEVEL) || \
|
|
((IT) == FSMC_IT_FALLING_EDGE) || \
|
|
((IT) == FSMC_IT_REFRESH_ERROR))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Flag_definition
|
|
* @brief FSMC Flag definition
|
|
* @{
|
|
*/
|
|
#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
|
|
#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
|
|
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
|
|
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
|
|
|
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
|
|
((FLAG) == FSMC_FLAG_LEVEL) || \
|
|
((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
|
|
((FLAG) == FSMC_FLAG_FEMPT))
|
|
|
|
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
|
|
|
|
/** @defgroup FSMC_NOR_Macros
|
|
* @brief macros to handle NOR device enable/disable and read/write operations
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the NORSRAM device access.
|
|
* @param __INSTANCE__: FSMC_NORSRAM Instance
|
|
* @param __BANK__: FSMC_NORSRAM Bank
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
|
|
|
|
/**
|
|
* @brief Disable the NORSRAM device access.
|
|
* @param __INSTANCE__: FSMC_NORSRAM Instance
|
|
* @param __BANK__: FSMC_NORSRAM Bank
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup FSMC_NAND_Macros
|
|
* @brief macros to handle NAND device enable/disable
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the NAND device access.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
|
|
((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
|
|
|
|
|
|
/**
|
|
* @brief Disable the NAND device access.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
|
|
((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_PCCARD_Macros
|
|
* @brief macros to handle SRAM read/write operations
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the PCCARD device access.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
|
|
|
|
/**
|
|
* @brief Disable the PCCARD device access.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @retval none
|
|
*/
|
|
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FSMC_Interrupt
|
|
* @brief macros to handle FSMC interrupts
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the NAND device interrupt.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __INTERRUPT__: FSMC_NAND interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
|
|
((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Disable the NAND device interrupt.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __INTERRUPT__: FSMC_NAND interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
|
|
((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
|
|
|
|
/**
|
|
* @brief Get flag status of the NAND device.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __FLAG__: FSMC_NAND flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval The state of FLAG (SET or RESET).
|
|
*/
|
|
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
|
|
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
|
|
/**
|
|
* @brief Clear flag status of the NAND device.
|
|
* @param __INSTANCE__: FSMC_NAND Instance
|
|
* @param __BANK__: FSMC_NAND Bank
|
|
* @param __FLAG__: FSMC_NAND flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
|
|
((__INSTANCE__)->SR3 &= ~(__FLAG__)))
|
|
/**
|
|
* @brief Enable the PCCARD device interrupt.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __INTERRUPT__: FSMC_PCCARD interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the PCCARD device interrupt.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __INTERRUPT__: FSMC_PCCARD interrupt
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
|
|
* @arg FSMC_IT_LEVEL: Interrupt level.
|
|
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
|
|
* @retval None
|
|
*/
|
|
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Get flag status of the PCCARD device.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __FLAG__: FSMC_PCCARD flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval The state of FLAG (SET or RESET).
|
|
*/
|
|
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
|
|
|
|
/**
|
|
* @brief Clear flag status of the PCCARD device.
|
|
* @param __INSTANCE__: FSMC_PCCARD Instance
|
|
* @param __FLAG__: FSMC_PCCARD flag
|
|
* This parameter can be any combination of the following values:
|
|
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
|
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
|
|
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
|
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
|
|
* @retval None
|
|
*/
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#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/* FSMC_NORSRAM Controller functions ******************************************/
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/* Initialization/de-initialization functions */
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HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
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HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
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HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
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HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
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/* FSMC_NORSRAM Control functions */
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HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
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HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
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/* FSMC_NAND Controller functions *********************************************/
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/* Initialization/de-initialization functions */
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HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
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HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
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HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
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HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
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/* FSMC_NAND Control functions */
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HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
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HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
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HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
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/* FSMC_PCCARD Controller functions *******************************************/
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/* Initialization/de-initialization functions */
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HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
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HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
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HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
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HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
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HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
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/* FSMC APIs, macros and typedefs redefinition */
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#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
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#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
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#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
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#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
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#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
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#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
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#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
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#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
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#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
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#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
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#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
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#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
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#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
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#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
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#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
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#define FMC_NAND_Init FSMC_NAND_Init
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#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
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#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
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#define FMC_NAND_DeInit FSMC_NAND_DeInit
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#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
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#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
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#define FMC_NAND_GetECC FSMC_NAND_GetECC
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#define FMC_PCCARD_Init FSMC_PCCARD_Init
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#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
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#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
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#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
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#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
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#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
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#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
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#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
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#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
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#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
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#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
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#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
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#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
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#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
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#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
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#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
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#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
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#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
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#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
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#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
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#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
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#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
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#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
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#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
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#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
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#define FMC_NAND_BANK2 FSMC_NAND_BANK2
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#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
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#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
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#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
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#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
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#define FMC_IT_LEVEL FSMC_IT_LEVEL
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#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
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#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
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#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
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#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
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#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
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#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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|
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/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
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|
|
#ifdef __cplusplus
|
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}
|
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#endif
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#endif /* __STM32F4xx_LL_FSMC_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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