104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2018-2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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#include "powerctrl.h"
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#if defined(STM32F0)
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void SystemClock_Config(void) {
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// Enable power control peripheral
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__HAL_RCC_PWR_CLK_ENABLE();
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// Set flash latency to 1 because SYSCLK > 24MHz
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FLASH->ACR = (FLASH->ACR & ~0x7) | 0x1;
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#if MICROPY_HW_CLK_USE_HSI48
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// Use the 48MHz internal oscillator
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RCC->CR2 |= RCC_CR2_HSI48ON;
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while ((RCC->CR2 & RCC_CR2_HSI48RDY) == 0) {
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}
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const uint32_t sysclk_src = 3;
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#else
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// Use HSE and the PLL to get a 48MHz SYSCLK
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#if MICROPY_HW_CLK_USE_BYPASS
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RCC->CR |= RCC_CR_HSEBYP;
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#endif
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0) {
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// Wait for HSE to be ready
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}
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RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
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RCC->CFGR2 = 0; // Input clock not divided
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RCC->CR |= RCC_CR_PLLON; // Turn PLL on
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
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// Wait for PLL to lock
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}
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const uint32_t sysclk_src = 2;
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#endif
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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}
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SystemCoreClockUpdate();
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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}
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#elif defined(STM32L0)
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void SystemClock_Config(void) {
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// Enable power control peripheral
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__HAL_RCC_PWR_CLK_ENABLE();
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// Use the 16MHz internal oscillator
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RCC->CR |= RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY)) {
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}
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const uint32_t sysclk_src = 1;
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// Select SYSCLK source
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RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
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while (((RCC->CFGR >> RCC_CFGR_SWS_Pos) & 0x3) != sysclk_src) {
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// Wait for SYSCLK source to change
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}
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SystemCoreClockUpdate();
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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}
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#endif
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