737 lines
41 KiB
C
737 lines
41 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_hal_flash_ex.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of FLASH HAL Extension module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_HAL_FLASH_EX_H
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#define __STM32F4xx_HAL_FLASH_EX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup FLASHEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief FLASH Erase structure definition
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*/
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typedef struct
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{
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uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase.
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This parameter can be a value of @ref FLASHEx_Type_Erase */
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uint32_t Banks; /*!< Banks: Select banks to erase when Mass erase is enabled
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This parameter must be a value of @ref FLASHEx_Banks */
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uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled
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This parameter must be a value of @ref FLASHEx_Sectors */
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uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased.
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This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
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uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism
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This parameter must be a value of @ref FLASHEx_Voltage_Range */
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} FLASH_EraseInitTypeDef;
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/**
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* @brief FLASH Option Bytes Program structure definition
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*/
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typedef struct
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{
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uint32_t OptionType; /*!< OptionType: Option byte to be configured.
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This parameter can be a value of @ref FLASHEx_Option_Type */
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uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
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This parameter can be a value of @ref FLASHEx_WRP_State */
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uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected
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The value of this parameter depend on device used within the same series */
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uint32_t Banks; /*!< Banks: Select banks for WRP activation/deactivation of all sectors
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This parameter must be a value of @ref FLASHEx_Banks */
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uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level..
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This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
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uint32_t BORLevel; /*!< BORLevel: Set the BOR Level.
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This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
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uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
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This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
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} FLASH_OBProgramInitTypeDef;
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/**
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* @brief FLASH Advanced Option Bytes Program structure definition
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
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typedef struct
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{
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uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
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This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
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uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
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This parameter can be a value of @ref FLASHEx_PCROP_State */
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#if defined (STM32F401xC) || defined (STM32F401xE)
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uint16_t Sectors; /*!< Sectors: specifies the sector(s) set for PCROP
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This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
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#endif /* STM32F401xC || STM32F401xE */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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uint32_t Banks; /*!< Banks: Select banks for PCROP activation/deactivation of all sectors
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This parameter must be a value of @ref FLASHEx_Banks */
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uint16_t SectorsBank1; /*!< SectorsBank1: specifies the sector(s) set for PCROP for Bank1
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This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
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uint16_t SectorsBank2; /*!< SectorsBank2: specifies the sector(s) set for PCROP for Bank2
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This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
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uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
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This parameter can be a value of @ref FLASHEx_Dual_Boot */
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#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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} FLASH_AdvOBProgramInitTypeDef;
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
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* @{
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*/
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/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
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* @{
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*/
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#define TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
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#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
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#define IS_TYPEERASE(VALUE)(((VALUE) == TYPEERASE_SECTORS) || \
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((VALUE) == TYPEERASE_MASSERASE))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
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* @{
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*/
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#define VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
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#define VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
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#define VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
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#define VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
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#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VOLTAGE_RANGE_1) || \
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((RANGE) == VOLTAGE_RANGE_2) || \
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((RANGE) == VOLTAGE_RANGE_3) || \
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((RANGE) == VOLTAGE_RANGE_4))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_WRP_State FLASH WRP State
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* @{
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*/
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#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
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#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
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#define IS_WRPSTATE(VALUE)(((VALUE) == WRPSTATE_DISABLE) || \
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((VALUE) == WRPSTATE_ENABLE))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Option_Type FLASH Option Type
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* @{
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*/
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#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
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#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
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#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
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#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
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#define IS_OPTIONBYTE(VALUE)(((VALUE) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
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* @{
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*/
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#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
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#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
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/*#define OB_RDP_LEVEL_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
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it s no more possible to go back to level 1 or 0 */
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#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
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((LEVEL) == OB_RDP_LEVEL_1))/*||\
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((LEVEL) == OB_RDP_LEVEL_2))*/
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
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* @{
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*/
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#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
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#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
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#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
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* @{
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*/
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#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
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#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
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#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
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* @{
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*/
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#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
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#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
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#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
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/**
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* @}
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*/
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/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
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* @{
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*/
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#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
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#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
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#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
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#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
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#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
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((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
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/**
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* @}
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
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/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
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* @{
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*/
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#define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable PCROP */
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#define PCROPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable PCROP */
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#define IS_PCROPSTATE(VALUE)(((VALUE) == PCROPSTATE_DISABLE) || \
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((VALUE) == PCROPSTATE_ENABLE))
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/**
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* @}
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*/
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
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/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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#define OBEX_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */
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#define OBEX_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */
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#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP) || \
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((VALUE) == OBEX_BOOTCONFIG))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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#if defined(STM32F401xC) || defined(STM32F401xE)
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#define OBEX_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration */
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#define IS_OBEX(VALUE)(((VALUE) == OBEX_PCROP))
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#endif /* STM32F401xC || STM32F401xE */
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/**
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* @}
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*/
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/** @defgroup FLASH_Latency FLASH Latency
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
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#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
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#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
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#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
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#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
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#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
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#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
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#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
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#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
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#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
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#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
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#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
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#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
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#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
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#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
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#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
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#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
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((LATENCY) == FLASH_LATENCY_1) || \
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((LATENCY) == FLASH_LATENCY_2) || \
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((LATENCY) == FLASH_LATENCY_3) || \
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((LATENCY) == FLASH_LATENCY_4) || \
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((LATENCY) == FLASH_LATENCY_5) || \
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((LATENCY) == FLASH_LATENCY_6) || \
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((LATENCY) == FLASH_LATENCY_7) || \
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((LATENCY) == FLASH_LATENCY_8) || \
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((LATENCY) == FLASH_LATENCY_9) || \
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((LATENCY) == FLASH_LATENCY_10) || \
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((LATENCY) == FLASH_LATENCY_11) || \
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((LATENCY) == FLASH_LATENCY_12) || \
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((LATENCY) == FLASH_LATENCY_13) || \
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((LATENCY) == FLASH_LATENCY_14) || \
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((LATENCY) == FLASH_LATENCY_15))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
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#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
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#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
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#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
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#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
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#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
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#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
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#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
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#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
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#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
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((LATENCY) == FLASH_LATENCY_1) || \
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((LATENCY) == FLASH_LATENCY_2) || \
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((LATENCY) == FLASH_LATENCY_3) || \
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((LATENCY) == FLASH_LATENCY_4) || \
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((LATENCY) == FLASH_LATENCY_5) || \
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((LATENCY) == FLASH_LATENCY_6) || \
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((LATENCY) == FLASH_LATENCY_7))
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#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Banks FLASH Banks
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
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#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
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#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
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#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
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((BANK) == FLASH_BANK_2) || \
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((BANK) == FLASH_BANK_BOTH))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
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#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
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#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
|
|
* @{
|
|
*/
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
|
|
|
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
|
|
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER Bit */
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FLASHEx_Sectors FLASH Sectors
|
|
* @{
|
|
*/
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
|
|
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
|
|
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
|
|
#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
|
|
#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
|
|
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
|
|
#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
|
|
#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
|
|
#define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */
|
|
#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
|
|
#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
|
|
#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
|
|
#define FLASH_SECTOR_12 ((uint32_t)12) /*!< Sector Number 12 */
|
|
#define FLASH_SECTOR_13 ((uint32_t)13) /*!< Sector Number 13 */
|
|
#define FLASH_SECTOR_14 ((uint32_t)14) /*!< Sector Number 14 */
|
|
#define FLASH_SECTOR_15 ((uint32_t)15) /*!< Sector Number 15 */
|
|
#define FLASH_SECTOR_16 ((uint32_t)16) /*!< Sector Number 16 */
|
|
#define FLASH_SECTOR_17 ((uint32_t)17) /*!< Sector Number 17 */
|
|
#define FLASH_SECTOR_18 ((uint32_t)18) /*!< Sector Number 18 */
|
|
#define FLASH_SECTOR_19 ((uint32_t)19) /*!< Sector Number 19 */
|
|
#define FLASH_SECTOR_20 ((uint32_t)20) /*!< Sector Number 20 */
|
|
#define FLASH_SECTOR_21 ((uint32_t)21) /*!< Sector Number 21 */
|
|
#define FLASH_SECTOR_22 ((uint32_t)22) /*!< Sector Number 22 */
|
|
#define FLASH_SECTOR_23 ((uint32_t)23) /*!< Sector Number 23 */
|
|
|
|
#define FLASH_SECTOR_TOTAL 24
|
|
|
|
#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
|
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
|
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
|
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
|
|
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
|
|
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
|
|
((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
|
|
((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
|
|
((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
|
|
((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
|
|
((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
|
|
((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
|
|
|
|
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
|
|
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
|
|
|
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
|
|
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
|
|
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
|
|
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
|
|
#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
|
|
#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
|
|
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
|
|
#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
|
|
#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
|
|
#define FLASH_SECTOR_8 ((uint32_t)8) /*!< Sector Number 8 */
|
|
#define FLASH_SECTOR_9 ((uint32_t)9) /*!< Sector Number 9 */
|
|
#define FLASH_SECTOR_10 ((uint32_t)10) /*!< Sector Number 10 */
|
|
#define FLASH_SECTOR_11 ((uint32_t)11) /*!< Sector Number 11 */
|
|
|
|
#define FLASH_SECTOR_TOTAL 12
|
|
|
|
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
|
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
|
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
|
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
|
|
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
|
|
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
|
|
|
|
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
|
|
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
|
|
|
#if defined(STM32F401xC)
|
|
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
|
|
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
|
|
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
|
|
#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
|
|
#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
|
|
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
|
|
|
|
#define FLASH_SECTOR_TOTAL 6
|
|
|
|
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
|
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
|
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5))
|
|
|
|
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\
|
|
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
|
|
#endif /* STM32F401xC */
|
|
|
|
#if defined(STM32F401xE)
|
|
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
|
|
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
|
|
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
|
|
#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
|
|
#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
|
|
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
|
|
#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
|
|
#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
|
|
|
|
#define FLASH_SECTOR_TOTAL 8
|
|
|
|
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
|
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
|
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
|
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
|
|
|
|
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) ||\
|
|
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
|
|
#endif /* STM32F401xE */
|
|
|
|
#define IS_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
|
* @{
|
|
*/
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
|
|
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
|
|
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
|
|
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
|
|
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
|
|
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
|
|
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
|
|
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
|
|
#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
|
|
#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
|
|
#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
|
|
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
|
|
#define OB_WRP_SECTOR_12 ((uint32_t)0x00000001 << 12) /*!< Write protection of Sector12 */
|
|
#define OB_WRP_SECTOR_13 ((uint32_t)0x00000002 << 12) /*!< Write protection of Sector13 */
|
|
#define OB_WRP_SECTOR_14 ((uint32_t)0x00000004 << 12) /*!< Write protection of Sector14 */
|
|
#define OB_WRP_SECTOR_15 ((uint32_t)0x00000008 << 12) /*!< Write protection of Sector15 */
|
|
#define OB_WRP_SECTOR_16 ((uint32_t)0x00000010 << 12) /*!< Write protection of Sector16 */
|
|
#define OB_WRP_SECTOR_17 ((uint32_t)0x00000020 << 12) /*!< Write protection of Sector17 */
|
|
#define OB_WRP_SECTOR_18 ((uint32_t)0x00000040 << 12) /*!< Write protection of Sector18 */
|
|
#define OB_WRP_SECTOR_19 ((uint32_t)0x00000080 << 12) /*!< Write protection of Sector19 */
|
|
#define OB_WRP_SECTOR_20 ((uint32_t)0x00000100 << 12) /*!< Write protection of Sector20 */
|
|
#define OB_WRP_SECTOR_21 ((uint32_t)0x00000200 << 12) /*!< Write protection of Sector21 */
|
|
#define OB_WRP_SECTOR_22 ((uint32_t)0x00000400 << 12) /*!< Write protection of Sector22 */
|
|
#define OB_WRP_SECTOR_23 ((uint32_t)0x00000800 << 12) /*!< Write protection of Sector23 */
|
|
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF << 12) /*!< Write protection of all Sectors */
|
|
|
|
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
|
|
|
|
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
|
|
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
|
|
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
|
|
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
|
|
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
|
|
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
|
|
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
|
|
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
|
|
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
|
|
#define OB_WRP_SECTOR_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
|
|
#define OB_WRP_SECTOR_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
|
|
#define OB_WRP_SECTOR_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
|
|
#define OB_WRP_SECTOR_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
|
|
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
|
|
|
|
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
|
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
|
|
|
#if defined(STM32F401xC)
|
|
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
|
|
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
|
|
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
|
|
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
|
|
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
|
|
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
|
|
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
|
|
|
|
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
|
#endif /* STM32F401xC */
|
|
|
|
#if defined(STM32F401xE)
|
|
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
|
|
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
|
|
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
|
|
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
|
|
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
|
|
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
|
|
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
|
|
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
|
|
#define OB_WRP_SECTOR_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
|
|
|
|
#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
|
#endif /* STM32F401xE */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
|
|
* @{
|
|
*/
|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
|
|
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
|
|
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
|
|
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
|
|
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
|
|
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
|
|
#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
|
|
#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
|
|
#define OB_PCROP_SECTOR_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
|
|
#define OB_PCROP_SECTOR_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
|
|
#define OB_PCROP_SECTOR_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
|
|
#define OB_PCROP_SECTOR_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
|
|
#define OB_PCROP_SECTOR_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
|
|
#define OB_PCROP_SECTOR_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
|
|
#define OB_PCROP_SECTOR_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
|
|
#define OB_PCROP_SECTOR_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
|
|
#define OB_PCROP_SECTOR_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
|
|
#define OB_PCROP_SECTOR_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
|
|
#define OB_PCROP_SECTOR_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
|
|
#define OB_PCROP_SECTOR_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
|
|
#define OB_PCROP_SECTOR_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
|
|
#define OB_PCROP_SECTOR_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
|
|
#define OB_PCROP_SECTOR_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
|
|
#define OB_PCROP_SECTOR_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
|
|
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
|
|
|
|
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
|
|
|
|
#if defined(STM32F401xC)
|
|
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
|
|
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
|
|
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
|
|
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
|
|
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
|
|
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
|
|
#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
|
|
|
|
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
|
#endif /* STM32F401xC */
|
|
|
|
#if defined(STM32F401xE)
|
|
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
|
|
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
|
|
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
|
|
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
|
|
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
|
|
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
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#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
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#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
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#define OB_PCROP_SECTOR_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
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#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
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#endif /* STM32F401xE */
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define OB_DUAL_BOOT_ENABLE ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
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#define OB_DUAL_BOOT_DISABLE ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
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#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
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/**
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* @}
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*/
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/** @defgroup FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
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* @{
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
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#define OB_PCROP_DESELECTED ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
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#define OB_PCROP_SELECTED ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
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#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
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/**
|
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* @}
|
|
*/
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/**
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* @brief OPTCR1 register byte 2 (Bits[23:16]) base address
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*/
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
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/**
|
|
* @}
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|
*/
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|
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/* Extension Program operation functions *************************************/
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HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
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HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
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HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
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void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
|
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HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
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void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
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HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
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|
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE */
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|
|
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
|
uint16_t HAL_FLASHEx_OB_GetBank2WRP(void);
|
|
#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
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|
|
|
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
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|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
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|
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#endif /* __STM32F4xx_HAL_FLASH_EX_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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