941 lines
42 KiB
C
941 lines
42 KiB
C
/**
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******************************************************************************
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* @file stm32f4xx_ll_sdmmc.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 18-February-2014
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* @brief Header file of SDMMC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_LL_SDMMC_H
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#define __STM32F4xx_LL_SDMMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hal_def.h"
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/** @addtogroup STM32F4xx_Driver
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* @{
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*/
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/** @addtogroup SDMMC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief SDMMC Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
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This parameter can be a value of @ref SDIO_Clock_Edge */
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uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
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enabled or disabled.
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This parameter can be a value of @ref SDIO_Clock_Bypass */
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uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
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disabled when the bus is idle.
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This parameter can be a value of @ref SDIO_Clock_Power_Save */
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uint32_t BusWide; /*!< Specifies the SDIO bus width.
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This parameter can be a value of @ref SDIO_Bus_Wide */
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uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
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This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
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uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
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This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
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}SDIO_InitTypeDef;
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/**
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* @brief SDIO Command Control structure
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*/
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typedef struct
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{
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uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
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to a card as part of a command message. If a command
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contains an argument, it must be loaded into this register
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before writing the command to the command register. */
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uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
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Max_Data = 64 */
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uint32_t Response; /*!< Specifies the SDIO response type.
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This parameter can be a value of @ref SDIO_Response_Type */
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uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
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enabled or disabled.
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This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
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uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
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is enabled or disabled.
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This parameter can be a value of @ref SDIO_CPSM_State */
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}SDIO_CmdInitTypeDef;
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/**
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* @brief SDIO Data Control structure
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*/
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typedef struct
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{
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uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
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uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
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uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
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This parameter can be a value of @ref SDIO_Data_Block_Size */
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uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
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is a read or write.
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This parameter can be a value of @ref SDIO_Transfer_Direction */
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uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
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This parameter can be a value of @ref SDIO_Transfer_Type */
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uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
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is enabled or disabled.
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This parameter can be a value of @ref SDIO_DPSM_State */
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}SDIO_DataInitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SDIO_Exported_Constants
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* @{
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*/
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/** @defgroup SDIO_Clock_Edge
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* @{
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*/
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#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
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#define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
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#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
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((EDGE) == SDIO_CLOCK_EDGE_FALLING))
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/**
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* @}
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*/
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/** @defgroup SDIO_Clock_Bypass
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* @{
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*/
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#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
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#define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
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#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
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((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDIO_Clock_Power_Save
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* @{
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*/
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#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
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#define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
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#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
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((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDIO_Bus_Wide
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* @{
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*/
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#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
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#define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
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#define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
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#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
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((WIDE) == SDIO_BUS_WIDE_4B) || \
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((WIDE) == SDIO_BUS_WIDE_8B))
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/**
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* @}
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*/
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/** @defgroup SDIO_Hardware_Flow_Control
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* @{
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*/
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#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
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#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
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#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
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((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDIO_Clock_Division
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* @{
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*/
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#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup SDIO_Command_Index
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* @{
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*/
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#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
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/**
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* @}
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*/
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/** @defgroup SDIO_Response_Type
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* @{
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*/
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#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
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#define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
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#define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
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#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
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((RESPONSE) == SDIO_RESPONSE_SHORT) || \
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((RESPONSE) == SDIO_RESPONSE_LONG))
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/**
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* @}
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*/
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/** @defgroup SDIO_Wait_Interrupt_State
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* @{
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*/
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#define SDIO_WAIT_NO ((uint32_t)0x00000000)
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#define SDIO_WAIT_IT ((uint32_t)0x00000100)
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#define SDIO_WAIT_PEND ((uint32_t)0x00000200)
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#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
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((WAIT) == SDIO_WAIT_IT) || \
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((WAIT) == SDIO_WAIT_PEND))
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/**
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* @}
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*/
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/** @defgroup SDIO_CPSM_State
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* @{
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*/
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#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
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#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
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#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
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((CPSM) == SDIO_CPSM_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDIO_Response_Registers
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* @{
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*/
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#define SDIO_RESP1 ((uint32_t)0x00000000)
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#define SDIO_RESP2 ((uint32_t)0x00000004)
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#define SDIO_RESP3 ((uint32_t)0x00000008)
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#define SDIO_RESP4 ((uint32_t)0x0000000C)
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#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
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((RESP) == SDIO_RESP2) || \
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((RESP) == SDIO_RESP3) || \
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((RESP) == SDIO_RESP4))
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/**
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* @}
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*/
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/** @defgroup SDIO_Data_Length
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* @{
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*/
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#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
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/**
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* @}
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*/
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/** @defgroup SDIO_Data_Block_Size
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* @{
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*/
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#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
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#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
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#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
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#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
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#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
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#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
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#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
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#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
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#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
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#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
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#define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
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#define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
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#define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
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#define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
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#define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
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#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
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((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
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/**
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* @}
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*/
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/** @defgroup SDIO_Transfer_Direction
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* @{
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*/
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#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
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#define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
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#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
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((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
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/**
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* @}
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*/
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/** @defgroup SDIO_Transfer_Type
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* @{
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*/
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#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
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#define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
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#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
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((MODE) == SDIO_TRANSFER_MODE_STREAM))
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/**
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* @}
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*/
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/** @defgroup SDIO_DPSM_State
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* @{
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*/
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#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
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#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
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#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
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((DPSM) == SDIO_DPSM_ENABLE))
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/**
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* @}
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*/
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/** @defgroup SDIO_Read_Wait_Mode
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* @{
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*/
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#define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
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#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
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#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
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((MODE) == SDIO_READ_WAIT_MODE_DATA2))
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/**
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* @}
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*/
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/** @defgroup SDIO_Interrupt_sources
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* @{
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*/
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#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
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#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
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#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
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#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
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#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
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#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
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#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
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#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
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#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
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#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
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#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
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#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
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#define SDIO_IT_TXACT ((uint32_t)0x00001000)
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#define SDIO_IT_RXACT ((uint32_t)0x00002000)
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#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
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#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
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#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
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#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
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#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
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#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
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#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
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#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
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#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
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#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
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#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
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/**
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* @}
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*/
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/** @defgroup SDIO_Flags
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* @{
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*/
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#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
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#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
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#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
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#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
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#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
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#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
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#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
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#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
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#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
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#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
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#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
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#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
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#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
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#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
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#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
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#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
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#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
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#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
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#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
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#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
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#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
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#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
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#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
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#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
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#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
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((FLAG) == SDIO_FLAG_DCRCFAIL) || \
|
|
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
|
|
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
|
|
((FLAG) == SDIO_FLAG_TXUNDERR) || \
|
|
((FLAG) == SDIO_FLAG_RXOVERR) || \
|
|
((FLAG) == SDIO_FLAG_CMDREND) || \
|
|
((FLAG) == SDIO_FLAG_CMDSENT) || \
|
|
((FLAG) == SDIO_FLAG_DATAEND) || \
|
|
((FLAG) == SDIO_FLAG_STBITERR) || \
|
|
((FLAG) == SDIO_FLAG_DBCKEND) || \
|
|
((FLAG) == SDIO_FLAG_CMDACT) || \
|
|
((FLAG) == SDIO_FLAG_TXACT) || \
|
|
((FLAG) == SDIO_FLAG_RXACT) || \
|
|
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
|
|
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
|
|
((FLAG) == SDIO_FLAG_TXFIFOF) || \
|
|
((FLAG) == SDIO_FLAG_RXFIFOF) || \
|
|
((FLAG) == SDIO_FLAG_TXFIFOE) || \
|
|
((FLAG) == SDIO_FLAG_RXFIFOE) || \
|
|
((FLAG) == SDIO_FLAG_TXDAVL) || \
|
|
((FLAG) == SDIO_FLAG_RXDAVL) || \
|
|
((FLAG) == SDIO_FLAG_SDIOIT) || \
|
|
((FLAG) == SDIO_FLAG_CEATAEND))
|
|
|
|
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
|
|
|
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
|
|
((IT) == SDIO_IT_DCRCFAIL) || \
|
|
((IT) == SDIO_IT_CTIMEOUT) || \
|
|
((IT) == SDIO_IT_DTIMEOUT) || \
|
|
((IT) == SDIO_IT_TXUNDERR) || \
|
|
((IT) == SDIO_IT_RXOVERR) || \
|
|
((IT) == SDIO_IT_CMDREND) || \
|
|
((IT) == SDIO_IT_CMDSENT) || \
|
|
((IT) == SDIO_IT_DATAEND) || \
|
|
((IT) == SDIO_IT_STBITERR) || \
|
|
((IT) == SDIO_IT_DBCKEND) || \
|
|
((IT) == SDIO_IT_CMDACT) || \
|
|
((IT) == SDIO_IT_TXACT) || \
|
|
((IT) == SDIO_IT_RXACT) || \
|
|
((IT) == SDIO_IT_TXFIFOHE) || \
|
|
((IT) == SDIO_IT_RXFIFOHF) || \
|
|
((IT) == SDIO_IT_TXFIFOF) || \
|
|
((IT) == SDIO_IT_RXFIFOF) || \
|
|
((IT) == SDIO_IT_TXFIFOE) || \
|
|
((IT) == SDIO_IT_RXFIFOE) || \
|
|
((IT) == SDIO_IT_TXDAVL) || \
|
|
((IT) == SDIO_IT_RXDAVL) || \
|
|
((IT) == SDIO_IT_SDIOIT) || \
|
|
((IT) == SDIO_IT_CEATAEND))
|
|
|
|
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup SDIO_Instance_definition
|
|
* @{
|
|
*/
|
|
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
/* ------------ SDIO registers bit address in the alias region -------------- */
|
|
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
|
|
|
/* --- CLKCR Register ---*/
|
|
/* Alias word address of CLKEN bit */
|
|
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
|
|
#define CLKEN_BitNumber 0x08
|
|
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
|
|
|
|
/* --- CMD Register ---*/
|
|
/* Alias word address of SDIOSUSPEND bit */
|
|
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
|
#define SDIOSUSPEND_BitNumber 0x0B
|
|
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
|
|
|
|
/* Alias word address of ENCMDCOMPL bit */
|
|
#define ENCMDCOMPL_BitNumber 0x0C
|
|
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
|
|
|
|
/* Alias word address of NIEN bit */
|
|
#define NIEN_BitNumber 0x0D
|
|
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
|
|
|
|
/* Alias word address of ATACMD bit */
|
|
#define ATACMD_BitNumber 0x0E
|
|
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
|
|
|
|
/* --- DCTRL Register ---*/
|
|
/* Alias word address of DMAEN bit */
|
|
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
|
#define DMAEN_BitNumber 0x03
|
|
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
|
|
|
|
/* Alias word address of RWSTART bit */
|
|
#define RWSTART_BitNumber 0x08
|
|
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
|
|
|
|
/* Alias word address of RWSTOP bit */
|
|
#define RWSTOP_BitNumber 0x09
|
|
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
|
|
|
|
/* Alias word address of RWMOD bit */
|
|
#define RWMOD_BitNumber 0x0A
|
|
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
|
|
|
|
/* Alias word address of SDIOEN bit */
|
|
#define SDIOEN_BitNumber 0x0B
|
|
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
|
|
|
|
/* ---------------------- SDIO registers bit mask --------------------------- */
|
|
/* --- CLKCR Register ---*/
|
|
/* CLKCR register clear mask */
|
|
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
|
|
|
/* --- PWRCTRL Register ---*/
|
|
/* SDIO PWRCTRL Mask */
|
|
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
|
|
|
/* --- DCTRL Register ---*/
|
|
/* SDIO DCTRL Clear Mask */
|
|
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
|
|
|
/* --- CMD Register ---*/
|
|
/* CMD Register clear mask */
|
|
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
|
|
|
/* SDIO RESP Registers Address */
|
|
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
|
|
|
/* SD FLASH SDIO Interface */
|
|
#define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
|
|
|
|
/* SDIO Intialization Frequency (400KHz max) */
|
|
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
|
|
|
|
/* SDIO Data Transfer Frequency (25MHz max) */
|
|
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
|
|
|
|
/** @defgroup SDIO_Interrupt_Clock
|
|
* @brief macros to handle interrupts and specific clock configurations
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable the SDIO device.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
|
|
|
|
/**
|
|
* @brief Disable the SDIO device.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
|
|
|
|
/**
|
|
* @brief Enable the SDIO DMA transfer.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
|
|
|
|
/**
|
|
* @brief Disable the SDIO DMA transfer.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
|
|
|
|
/**
|
|
* @brief Enable the SDIO device interrupt.
|
|
* @param __INSTANCE__ : Pointer to SDIO register base
|
|
* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the SDIO device interrupt.
|
|
* @param __INSTANCE__ : Pointer to SDIO register base
|
|
* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Checks whether the specified SDIO flag is set or not.
|
|
* @param __INSTANCE__ : Pointer to SDIO register base
|
|
* @param __FLAG__: specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
|
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
|
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
|
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
|
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
|
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
|
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
|
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
|
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
|
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
|
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
|
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
|
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
* @retval The new state of SDIO_FLAG (SET or RESET).
|
|
*/
|
|
#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
|
|
|
|
|
|
/**
|
|
* @brief Clears the SDIO's pending flags.
|
|
* @param __INSTANCE__ : Pointer to SDIO register base
|
|
* @param __FLAG__: specifies the flag to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
|
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
|
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
|
|
|
|
/**
|
|
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
|
* @param __INSTANCE__ : Pointer to SDIO register base
|
|
* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
|
* @retval The new state of SDIO_IT (SET or RESET).
|
|
*/
|
|
#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Clears the SDIO's interrupt pending bits.
|
|
* @param __INSTANCE__ : Pointer to SDIO register base
|
|
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Enable Start the SD I/O Read Wait operation.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
|
|
|
|
/**
|
|
* @brief Disable Start the SD I/O Read Wait operations.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
|
|
|
|
/**
|
|
* @brief Enable Start the SD I/O Read Wait operation.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
|
|
|
|
/**
|
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* @brief Disable Stop the SD I/O Read Wait operations.
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* @param None
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* @retval None
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*/
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#define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
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/**
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* @brief Enable the SD I/O Mode Operation.
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* @param None
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* @retval None
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*/
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#define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
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/**
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* @brief Disable the SD I/O Mode Operation.
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* @param None
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* @retval None
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*/
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#define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
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/**
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* @brief Enable the SD I/O Suspend command sending.
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* @param None
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* @retval None
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*/
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#define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
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/**
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* @brief Disable the SD I/O Suspend command sending.
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* @param None
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* @retval None
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*/
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#define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
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/**
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* @brief Enable the command completion signal.
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* @param None
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* @retval None
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*/
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#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
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/**
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* @brief Disable the command completion signal.
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* @param None
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* @retval None
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*/
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#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
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/**
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* @brief Enable the CE-ATA interrupt.
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* @param None
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* @retval None
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*/
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#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
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/**
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* @brief Disable the CE-ATA interrupt.
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* @param None
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* @retval None
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*/
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#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
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/**
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* @brief Enable send CE-ATA command (CMD61).
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* @param None
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* @retval None
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*/
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#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
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/**
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* @brief Disable send CE-ATA command (CMD61).
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* @param None
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* @retval None
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*/
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#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/* Initialization/de-initialization functions **********************************/
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HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
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/* I/O operation functions *****************************************************/
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/* Blocking mode: Polling */
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uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
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HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
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/* Peripheral Control functions ************************************************/
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HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
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HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
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uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
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/* Command path state machine (CPSM) management functions */
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HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
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uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
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uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
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/* Data path state machine (DPSM) management functions */
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HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
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uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
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uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
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/* SDIO IO Cards mode management functions */
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HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F4xx_LL_SDMMC_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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