520 lines
29 KiB
C
520 lines
29 KiB
C
//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_CAMERA_H__
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#define __HW_CAMERA_H__
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//*****************************************************************************
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//
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// The following are defines for the CAMERA register offsets.
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//
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//*****************************************************************************
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#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP
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// revision code ( Parallel Mode)
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#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the
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// various parameters of the OCP
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// interface (CCP and Parallel Mode)
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#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status
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// information about the module
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// excluding the interrupt status
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// information (CCP and Parallel
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// Mode)
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#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups
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// all the status of the module
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// internal events that can generate
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// an interrupt (CCP & Parallel
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// Mode)
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#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register
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// allows to enable/disable the
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// module internal sources of
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// interrupt on an event-by-event
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// basis (CCP & Parallel Mode)
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#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the
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// various parameters of the Camera
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// Core block (CCP & Parallel Mode)
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#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA
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// interface of the Camera Core
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// block (CCP & Parallel Mode)
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#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value
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// of the clock divisor used to
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// generate the external clock
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// (Parallel Mode)
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#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to
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// the FIFO and read from the FIFO
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// (CCP & Parallel Mode)
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#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status
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// of some important variables of
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// the camera core module (CCP &
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// Parallel Mode)
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#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values
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// of the generic parameters of the
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// module
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_REVISION register.
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//
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//******************************************************************************
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#define CAMERA_CC_REVISION_REV_M \
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0x000000FF // IP revision [7:4] Major revision
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// [3:0] Minor revision Examples:
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// 0x10 for 1.0 0x21 for 2.1
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#define CAMERA_CC_REVISION_REV_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_SYSCONFIG register.
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//
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//******************************************************************************
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#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
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0x00000018 // Slave interface power management
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// req/ack control """00""
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// Force-idle. An idle request is
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// acknoledged unconditionally"
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// """01"" No-idle. An idle request
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// is never acknowledged" """10""
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// reserved (Smart-idle not
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// implemented)"
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#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
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#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
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0x00000002 // Software reset. Set this bit to
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// 1 to trigger a module reset. The
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// bit is automatically reset by the
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// hardware. During reset it always
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// returns 0. 0 Normal mode 1 The
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// module is reset
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#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
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0x00000001 // Internal OCP clock gating
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// strategy 0 OCP clock is
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// free-running 1 Automatic OCP
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// clock gating strategy is applied
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// based on the OCP interface
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// activity
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_SYSSTATUS register.
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//
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//******************************************************************************
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#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
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0x00000001 // Internal Reset Monitoring 0
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// Internal module reset is on-going
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// 1 Reset completed
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_IRQSTATUS register.
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//
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//******************************************************************************
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#define CAMERA_CC_IRQSTATUS_FS_IRQ \
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0x00080000 // Frame Start has occurred 0 Event
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// false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_LE_IRQ \
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0x00040000 // Line End has occurred 0 Event
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// false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_LS_IRQ \
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0x00020000 // Line Start has occurred 0 Event
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// false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_FE_IRQ \
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0x00010000 // Frame End has occurred 0 Event
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// false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
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0x00000800 // FSP code error 0 Event false "1
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// Event is true (""pending"")" 0
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// Event status bit unchanged 1
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// Event status bit is reset
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#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
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0x00000400 // Frame Height Error 0 Event false
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// "1 Event is true (""pending"")" 0
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// Event status bit unchanged 1
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// Event status bit is reset
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#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
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0x00000200 // False Synchronization Code 0
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// Event false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
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0x00000100 // Shifted Synchronization Code 0
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// Event false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
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0x00000010 // FIFO is not empty 0 Event false
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// "1 Event is true (""pending"")" 0
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// Event status bit unchanged 1
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// Event status bit is reset
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#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
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0x00000008 // FIFO is full 0 Event false "1
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// Event is true (""pending"")" 0
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// Event status bit unchanged 1
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// Event status bit is reset
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#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
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0x00000004 // FIFO threshold has been reached
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// 0 Event false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
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0x00000002 // FIFO overflow has occurred 0
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// Event false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
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0x00000001 // FIFO underflow has occurred 0
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// Event false "1 Event is true
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// (""pending"")" 0 Event status bit
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// unchanged 1 Event status bit is
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// reset
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_IRQENABLE register.
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//
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//******************************************************************************
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#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
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0x00080000 // Frame Start Interrupt Enable 0
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// Event is masked 1 Event generates
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// an interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
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0x00040000 // Line End Interrupt Enable 0
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// Event is masked 1 Event generates
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// an interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
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0x00020000 // Line Start Interrupt Enable 0
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// Event is masked 1 Event generates
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// an interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
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0x00010000 // Frame End Interrupt Enable 0
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// Event is masked 1 Event generates
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// an interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
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0x00000800 // FSP code Interrupt Enable 0
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// Event is masked 1 Event generates
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// an interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
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0x00000400 // Frame Height Error Interrupt
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// Enable 0 Event is masked 1 Event
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// generates an interrupt when it
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// occurs
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#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
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0x00000200 // False Synchronization Code
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// Interrupt Enable 0 Event is
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// masked 1 Event generates an
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// interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
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0x00000100 // False Synchronization Code
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// Interrupt Enable 0 Event is
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// masked 1 Event generates an
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// interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
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0x00000010 // FIFO Threshold Interrupt Enable
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// 0 Event is masked 1 Event
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// generates an interrupt when it
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// occurs
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#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
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0x00000008 // FIFO Threshold Interrupt Enable
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// 0 Event is masked 1 Event
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// generates an interrupt when it
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// occurs
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#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
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0x00000004 // FIFO Threshold Interrupt Enable
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// 0 Event is masked 1 Event
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// generates an interrupt when it
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// occurs
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#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
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0x00000002 // FIFO Overflow Interrupt Enable 0
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// Event is masked 1 Event generates
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// an interrupt when it occurs
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#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
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0x00000001 // FIFO Underflow Interrupt Enable
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// 0 Event is masked 1 Event
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// generates an interrupt when it
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// occurs
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//******************************************************************************
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//
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// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
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//
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//******************************************************************************
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#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
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0x00080000 // Synchronize all camera sensor
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// inputs This must be set during
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// the configuration phase before
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// CC_EN set to '1'. This can be
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// used in very high frequency to
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// avoid dependancy to the IO
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// timings. 0 No synchro (most of
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// applications) 1 Synchro enabled
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// (should never be required)
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#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite
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// states machines of the camera
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// core module - by writing a 1 to
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// this bit. must be applied when
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// CC_EN = 0 Reads returns 0
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#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
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0x00020000 // Set the modality in which CC_EN
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// works when a disabling of the
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// sensor camera core is wanted "If
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// CC_FRAME_TRIG = 1 by writing
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// ""0"" to CC_EN" the module is
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// disabled at the end of the frame
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// "If CC_FRAME_TRIG = 0 by writing
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// ""0"" to CC_EN" the module is
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// disabled immediately
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#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of
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// the camera core module "By
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// writing ""1"" to this field the
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// module is enabled." "By writing
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// ""0"" to this field the module is
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// disabled at" the end of the frame
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// if CC_FRAM_TRIG =1 and is
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// disabled immediately if
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// CC_FRAM_TRIG = 0
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#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
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0x00002000 // Enables to start at the
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// beginning of the frame or not in
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// NoBT 0 Acquisition starts when
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// Vertical synchro is high 1
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// Acquisition starts when Vertical
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// synchro goes from low to high
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// (beginning of the frame) -
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// Recommended.
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#define CAMERA_CC_CTRL_BT_CORRECT \
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0x00001000 // Enables the correction within
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// the sync codes in BT mode 0
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// correction is not enabled 1
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// correction is enabled
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#define CAMERA_CC_CTRL_PAR_ORDERCAM \
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0x00000800 // Enables swap between image-data
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// in parallel mode 0 swap is not
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// enabled 1 swap is enabled
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#define CAMERA_CC_CTRL_PAR_CLK_POL \
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0x00000400 // Inverts the clock coming from
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// the sensor in parallel mode 0
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// clock not inverted - data sampled
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// on rising edge 1 clock inverted -
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// data sampled on falling edge
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#define CAMERA_CC_CTRL_NOBT_HS_POL \
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0x00000200 // Sets the polarity of the
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// synchronization signals in NOBT
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// parallel mode 0 CAM_P_HS is
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// active high 1 CAM_P_HS is active
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// low
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#define CAMERA_CC_CTRL_NOBT_VS_POL \
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0x00000100 // Sets the polarity of the
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// synchronization signals in NOBT
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// parallel mode 0 CAM_P_VS is
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// active high 1 CAM_P_VS is active
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// low
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#define CAMERA_CC_CTRL_PAR_MODE_M \
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0x0000000E // Sets the Protocol Mode of the
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// Camera Core module in parallel
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// mode (when CCP_MODE = 0) """000""
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// Parallel NOBT 8-bit" """001""
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// Parallel NOBT 10-bit" """010""
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// Parallel NOBT 12-bit" """011""
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// reserved" """100"" Parallet BT
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// 8-bit" """101"" Parallel BT
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// 10-bit" """110"" reserved"
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// """111"" FIFO test mode. Refer to
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// Table 12 - FIFO Write and Read
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// access"
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#define CAMERA_CC_CTRL_PAR_MODE_S 1
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#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode
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// 0 CCP mode disabled 1 CCP mode
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// enabled
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_CTRL_DMA register.
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//
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//******************************************************************************
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#define CAMERA_CC_CTRL_DMA_DMA_EN \
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0x00000100 // Sets the number of dma request
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// lines 0 DMA interface disabled
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// The DMA request line stays
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// inactive 1 DMA interface enabled
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// The DMA request line is
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// operational
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#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
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0x0000007F // Sets the threshold of the FIFO
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// the assertion of the dmarequest
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// line takes place when the
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// threshold is reached.
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// """0000000"" threshold set to 1"
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// """0000001"" threshold set to 2"
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// … """1111111"" threshold set to
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// 128"
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#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_CTRL_XCLK register.
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//
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//******************************************************************************
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#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
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0x0000001F // Sets the clock divisor value for
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// CAM_XCLK generation. based on
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// CAM_MCK (value of CAM_MCLK is
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// 96MHz) """00000"" CAM_XCLK Stable
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// Low Level" Divider not enabled
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// """00001"" CAM_XCLK Stable High
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// Level" Divider not enabled from 2
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// to 30 CAM_XCLK = CAM_MCLK /
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// XCLK_DIV """11111"" Bypass -
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// CAM_XCLK = CAM_MCLK"
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#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_FIFO_DATA register.
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//
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//******************************************************************************
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#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
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0xFFFFFFFF // Writes the 32-bit word into the
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// FIFO Reads the 32-bit word from
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// the FIFO
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#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
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//
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//******************************************************************************
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#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
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0xFF000000 // FIFO READ Pointer This field
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// shows the value of the FIFO read
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// pointer Expected value ranges
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// from 0 to 127
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#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
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#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
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0x00FF0000 // FIFO WRITE pointer This field
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// shows the value of the FIFO write
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// pointer Expected value ranges
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// from 0 to 127
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#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
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#define CAMERA_CC_TEST_FIFO_LEVEL_M \
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0x0000FF00 // FIFO level (how many 32-bit
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// words the FIFO contains) This
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// field shows the value of the FIFO
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// level and can assume values from
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// 0 to 128
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#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
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#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
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0x000000FF // FIFO level peak This field shows
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// the max value of the FIFO level
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// and can assume values from 0 to
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// 128
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#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// CAMERA_O_CC_GEN_PAR register.
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//
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//******************************************************************************
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#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
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0x00000007 // Camera Core FIFO DEPTH generic
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// parameter
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#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
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#endif // __HW_CAMERA_H__
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