104 lines
4.0 KiB
C
104 lines
4.0 KiB
C
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2015 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// These are ordered by DMAx_Stream number, and within a stream by channel
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// number. The duplicate streams are ok as long as they aren't used at the
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// same time.
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//
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// Currently I2C and SPI are synchronous and they call dma_init/dma_deinit
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// around each transfer.
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// DMA1 streams
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#define DMA_STREAM_I2C1_RX DMA1_Stream0
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#define DMA_CHANNEL_I2C1_RX DMA_CHANNEL_1
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#define DMA_STREAM_SPI3_RX DMA1_Stream2
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#define DMA_CHANNEL_SPI3_RX DMA_CHANNEL_0
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#define DMA_STREAM_I2C3_RX DMA1_Stream2
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#define DMA_CHANNEL_I2C3_RX DMA_CHANNEL_3
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#define DMA_STREAM_I2C2_RX DMA1_Stream2
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#define DMA_CHANNEL_I2C2_RX DMA_CHANNEL_7
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#define DMA_STREAM_SPI2_RX DMA1_Stream3
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#define DMA_CHANNEL_SPI2_RX DMA_CHANNEL_0
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#define DMA_STREAM_SPI2_TX DMA1_Stream4
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#define DMA_CHANNEL_SPI2_TX DMA_CHANNEL_0
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#define DMA_STREAM_I2C3_TX DMA1_Stream4
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#define DMA_CHANNEL_I2C3_TX DMA_CHANNEL_3
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#define DMA_STREAM_DAC1 DMA1_Stream5
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#define DMA_CHANNEL_DAC1 DMA_CHANNEL_7
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#define DMA_STREAM_DAC2 DMA1_Stream6
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#define DMA_CHANNEL_DAC2 DMA_CHANNEL_7
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#define DMA_STREAM_SPI3_TX DMA1_Stream7
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#define DMA_CHANNEL_SPI3_TX DMA_CHANNEL_0
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#define DMA_STREAM_I2C1_TX DMA1_Stream7
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#define DMA_CHANNEL_I2C1_TX DMA_CHANNEL_1
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#define DMA_STREAM_I2C2_TX DMA1_Stream7
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#define DMA_CHANNEL_I2C2_TX DMA_CHANNEL_7
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// DMA2 streams
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#define DMA_STREAM_SPI1_RX DMA2_Stream2
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#define DMA_CHANNEL_SPI1_RX DMA_CHANNEL_3
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#define DMA_STREAM_SDIO_RX DMA2_Stream3
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#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4
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#define DMA_STREAM_SPI1_TX DMA2_Stream5
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#define DMA_CHANNEL_SPI1_TX DMA_CHANNEL_3
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#define DMA_STREAM_SDIO_TX DMA2_Stream6
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#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4
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typedef union {
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uint16_t enabled; // Used to test if both counters are == 0
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uint8_t counter[2];
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} dma_idle_count_t;
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extern volatile dma_idle_count_t dma_idle;
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#define DMA_IDLE_ENABLED() (dma_idle.enabled != 0)
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#define DMA_SYSTICK_MASK 0x0e
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#define DMA_MSECS_PER_SYSTICK (DMA_SYSTICK_MASK + 1)
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#define DMA_IDLE_TICK_MAX (8) // 128 msec
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#define DMA_IDLE_TICK(tick) (((tick) & DMA_SYSTICK_MASK) == 0)
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extern const DMA_InitTypeDef dma_init_struct_spi_i2c;
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void dma_init(DMA_HandleTypeDef *dma, DMA_Stream_TypeDef *dma_stream, const DMA_InitTypeDef *dma_init, uint32_t dma_channel, uint32_t direction, void *data);
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void dma_deinit(DMA_HandleTypeDef *dma);
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void dma_invalidate_channel(DMA_Stream_TypeDef *dma_stream, uint32_t dma_channel);
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void dma_idle_handler(int controller);
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