751 lines
17 KiB
C
751 lines
17 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Renesas Electronics Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal_data.h"
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#include "ra_config.h"
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#include "ra_gpio.h"
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#include "ra_int.h"
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#include "ra_timer.h"
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#include "ra_icu.h"
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#define DEFAULT_BOUNCE_PERIOD (200) /* 200ms */
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#if !defined(RA_PRI_EXTIT)
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#define RA_PRI_EXTINT (14)
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#endif
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static R_ICU_Type *icu_reg = (R_ICU_Type *)0x40006000;
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enum
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{
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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IRQ0_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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IRQ1_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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IRQ2_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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IRQ3_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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IRQ4_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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IRQ5_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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IRQ6_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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IRQ7_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ8)
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IRQ8_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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IRQ9_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ10)
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IRQ10_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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IRQ11_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ12)
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IRQ12_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ13)
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IRQ13_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ14)
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IRQ14_IDX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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IRQ15_IDX,
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#endif
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IRQ_IDX_MAX,
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};
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static const ra_icu_pin_t ra_irq_pins[] = {
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#if defined(RA4W1)
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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{ 0, P105 },
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{ 0, P206 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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{ 1, P101 },
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{ 1, P104 },
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{ 1, P205 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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{ 2, P100 },
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{ 2, P213 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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{ 3, P004 },
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{ 3, P110 },
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{ 3, P212 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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{ 4, P111 },
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{ 4, P402 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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{ 6, P409 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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{ 7, P015 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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{ 9, P414 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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{ 11, P501 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ14)
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{ 14, P010 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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{ 15, P011 },
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#endif
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#elif defined(RA4M1)
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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{ 0, P105 },
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{ 0, P206 },
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{ 0, P400 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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{ 1, P101 },
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{ 1, P104 },
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{ 1, P205 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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{ 2, P002 },
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{ 2, P100 },
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{ 2, P213 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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{ 3, P004 },
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{ 3, P110 },
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{ 3, P212 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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{ 4, P111 },
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{ 4, P411 },
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{ 4, P402 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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{ 5, P302 },
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{ 5, P410 },
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{ 5, P401 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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{ 6, P000 },
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{ 6, P301 },
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{ 6, P409 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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{ 7, P001 },
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{ 7, P015 },
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{ 7, P408 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ8)
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{ 8, P305 },
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{ 8, P415 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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{ 9, P304 },
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{ 9, P414 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ10)
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{ 10, P005 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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{ 11, P501 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ12)
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{ 12, P502 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ14)
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{ 14, P505 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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{ 15, P011 },
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#endif
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#elif defined(RA6M1)
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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{ 0, P105 },
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{ 0, P206 }, /* DS */
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{ 0, P400 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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{ 1, P101 },
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{ 1, P104 },
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{ 1, P205 }, /* DS */
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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{ 2, P100 },
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{ 2, P213 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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{ 3, P110 },
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{ 3, P212 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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{ 4, P111 },
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{ 4, P402 }, /* DS */
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{ 4, P411 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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{ 5, P302 },
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{ 5, P401 }, /* DS */
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{ 5, P410 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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{ 6, P000 }, /* DS */
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{ 6, P301 },
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{ 6, P409 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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{ 7, P001 }, /* DS */
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{ 7, P408 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ8)
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{ 8, P002 }, /* DS */
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{ 8, P305 },
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{ 8, P415 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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{ 9, P004 }, /* DS */
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{ 9, P304 },
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{ 9, P414 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ10)
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{ 10, P005 }, /* DS */
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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{ 11, P006 }, /* DS */
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{ 11, P501 },
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{ 11, P708 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ12)
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{ 12, P008 }, /* DS */
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{ 12, P502 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ13)
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{ 13, P015 },
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#endif
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#elif defined(RA6M2)
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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{ 0, P105 },
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{ 0, P206 }, /* DS */
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{ 0, P400 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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{ 1, P101 },
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{ 1, P104 },
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{ 1, P205 }, /* DS */
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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{ 2, P100 },
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{ 2, P213 },
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{ 2, P203 }, /* DS */
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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{ 3, P110 },
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{ 3, P212 },
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{ 3, P202 }, /* DS */
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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{ 4, P111 },
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{ 4, P402 }, /* DS */
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{ 4, P411 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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{ 5, P302 },
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{ 5, P401 }, /* DS */
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{ 5, P410 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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{ 6, P000 }, /* DS */
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{ 6, P301 },
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{ 6, P409 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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{ 7, P001 }, /* DS */
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{ 7, P408 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ8)
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{ 8, P002 }, /* DS */
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{ 8, P305 },
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{ 8, P415 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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{ 9, P004 }, /* DS */
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{ 9, P304 },
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{ 9, P414 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ10)
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{ 10, P005 }, /* DS */
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{ 10, P709 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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{ 11, P006 }, /* DS */
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{ 11, P501 },
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{ 11, P708 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ12)
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{ 12, P008 }, /* DS */
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{ 12, P502 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ13)
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{ 13, P009 }, /* DS */
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{ 13, P015 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ14)
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{ 14, P505 },
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{ 14, P512 },
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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{ 15, P506 },
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{ 15, P511 },
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#endif
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#else
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#error "CMSIS MCU Series is not speficied."
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#endif
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};
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#define ICU_PINS_SIZE (sizeof(ra_irq_pins) / sizeof(ra_icu_pin_t))
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static const uint32_t idx_to_irq_vec[] = {
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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VECTOR_NUMBER_ICU_IRQ0,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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VECTOR_NUMBER_ICU_IRQ1,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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VECTOR_NUMBER_ICU_IRQ2,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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VECTOR_NUMBER_ICU_IRQ3,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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VECTOR_NUMBER_ICU_IRQ4,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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VECTOR_NUMBER_ICU_IRQ5,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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VECTOR_NUMBER_ICU_IRQ6,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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VECTOR_NUMBER_ICU_IRQ7,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ8)
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VECTOR_NUMBER_ICU_IRQ8,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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VECTOR_NUMBER_ICU_IRQ9,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ10)
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VECTOR_NUMBER_ICU_IRQ10,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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VECTOR_NUMBER_ICU_IRQ11,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ12)
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VECTOR_NUMBER_ICU_IRQ12,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ13)
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VECTOR_NUMBER_ICU_IRQ13,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ14)
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VECTOR_NUMBER_ICU_IRQ14,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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VECTOR_NUMBER_ICU_IRQ15,
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#endif
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};
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static const uint8_t irq_no_to_idx[] = {
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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IRQ0_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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IRQ1_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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IRQ2_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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IRQ3_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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IRQ4_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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IRQ5_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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IRQ6_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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IRQ7_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ8)
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IRQ8_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ9)
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IRQ9_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ10)
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IRQ10_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ11)
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IRQ11_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ12)
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IRQ12_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ13)
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IRQ13_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ14)
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IRQ14_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ15)
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IRQ15_IDX,
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#else
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IRQ_IDX_MAX,
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#endif
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};
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static const uint8_t irq_no_to_irq_vec[] = {
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#if defined(VECTOR_NUMBER_ICU_IRQ0)
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VECTOR_NUMBER_ICU_IRQ0,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ1)
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VECTOR_NUMBER_ICU_IRQ1,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ2)
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VECTOR_NUMBER_ICU_IRQ2,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ3)
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VECTOR_NUMBER_ICU_IRQ3,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ4)
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VECTOR_NUMBER_ICU_IRQ4,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ5)
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VECTOR_NUMBER_ICU_IRQ5,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ6)
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VECTOR_NUMBER_ICU_IRQ6,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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#if defined(VECTOR_NUMBER_ICU_IRQ7)
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VECTOR_NUMBER_ICU_IRQ7,
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#else
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VECTOR_NUMBER_NONE,
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#endif
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|
#if defined(VECTOR_NUMBER_ICU_IRQ8)
|
|
VECTOR_NUMBER_ICU_IRQ8,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ9)
|
|
VECTOR_NUMBER_ICU_IRQ9,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ10)
|
|
VECTOR_NUMBER_ICU_IRQ10,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ11)
|
|
VECTOR_NUMBER_ICU_IRQ11,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ12)
|
|
VECTOR_NUMBER_ICU_IRQ12,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ13)
|
|
VECTOR_NUMBER_ICU_IRQ13,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ14)
|
|
VECTOR_NUMBER_ICU_IRQ14,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
#if defined(VECTOR_NUMBER_ICU_IRQ15)
|
|
VECTOR_NUMBER_ICU_IRQ15,
|
|
#else
|
|
VECTOR_NUMBER_NONE,
|
|
#endif
|
|
};
|
|
static ICU_CB icu_cbs[IRQ_IDX_MAX];
|
|
static void *icu_params[IRQ_IDX_MAX];
|
|
static bool bounce_flag[IRQ_IDX_MAX];
|
|
static uint32_t bounce_period[IRQ_IDX_MAX];
|
|
static uint32_t bounce_start[IRQ_IDX_MAX];
|
|
|
|
bool ra_icu_find_irq_no(uint32_t pin, uint8_t *irq_no) {
|
|
ra_icu_pin_t *icu_pin = (ra_icu_pin_t *)&ra_irq_pins;
|
|
uint32_t size = (uint32_t)ICU_PINS_SIZE;
|
|
bool find = false;
|
|
uint32_t i;
|
|
for (i = 0; i < size; i++) {
|
|
if (icu_pin->pin == pin) {
|
|
find = true;
|
|
*irq_no = icu_pin->irq_no;
|
|
break;
|
|
}
|
|
icu_pin++;
|
|
}
|
|
return find;
|
|
}
|
|
|
|
static void ra_icu_irq_no(uint8_t irq_no, bool enable) {
|
|
uint8_t irq_vec = irq_no_to_irq_vec[irq_no];
|
|
if (irq_vec != VECTOR_NUMBER_NONE) {
|
|
if (enable) {
|
|
R_BSP_IrqCfg((IRQn_Type const)irq_vec, (uint32_t)RA_PRI_EXTINT, (void *)NULL);
|
|
R_BSP_IrqEnable((IRQn_Type const)irq_vec);
|
|
} else {
|
|
R_BSP_IrqDisable((IRQn_Type const)irq_vec);
|
|
}
|
|
}
|
|
}
|
|
|
|
void ra_icu_set_pin(uint32_t pin, bool irq_enable, bool pullup) {
|
|
uint32_t port = GPIO_PORT(pin);
|
|
uint32_t bit = GPIO_BIT(pin);
|
|
uint32_t pfs = _PXXPFS(port, bit);
|
|
pwpr_unprotect();
|
|
pfs &= ~PMR_MASK; /* GPIO */
|
|
pfs &= ~PDR_MASK; /* input */
|
|
if (irq_enable) {
|
|
pfs |= ISEL_MASK; /* set pullup */
|
|
} else {
|
|
pfs &= ~ISEL_MASK; /* clear pullup */
|
|
}
|
|
if (pullup) {
|
|
pfs |= PCR_MASK; /* set pullup */
|
|
} else {
|
|
pfs &= ~PCR_MASK; /* clear pullup */
|
|
}
|
|
_PXXPFS(port, bit) = pfs;
|
|
pwpr_protect();
|
|
}
|
|
|
|
static void ra_icu_pin(uint32_t pin, bool enable) {
|
|
bool find = false;
|
|
uint8_t irq_no;
|
|
find = ra_icu_find_irq_no(pin, &irq_no);
|
|
if (find) {
|
|
ra_icu_irq_no(irq_no, enable);
|
|
}
|
|
}
|
|
|
|
void ra_icu_enable_irq_no(uint8_t irq_no) {
|
|
ra_icu_irq_no(irq_no, true);
|
|
}
|
|
|
|
void ra_icu_disable_irq_no(uint8_t irq_no) {
|
|
ra_icu_irq_no(irq_no, false);
|
|
}
|
|
|
|
void ra_icu_enable_pin(uint32_t pin) {
|
|
ra_icu_pin(pin, true);
|
|
}
|
|
|
|
void ra_icu_disable_pin(uint32_t pin) {
|
|
ra_icu_pin(pin, false);
|
|
}
|
|
|
|
void ra_icu_priority_irq_no(uint8_t irq_no, uint32_t ipl) {
|
|
uint8_t irq_vec = (uint8_t)idx_to_irq_vec[irq_no];
|
|
R_BSP_IrqCfg((IRQn_Type const)irq_vec, ipl, (void *)NULL);
|
|
}
|
|
|
|
void ra_icu_priority_pin(uint32_t pin, uint32_t ipl) {
|
|
bool find = false;
|
|
uint8_t irq_no;
|
|
find = ra_icu_find_irq_no(pin, &irq_no);
|
|
if (find) {
|
|
ra_icu_priority_irq_no(irq_no, ipl);
|
|
}
|
|
}
|
|
|
|
void ra_icu_set_callback(uint8_t irq_no, ICU_CB func, void *param) {
|
|
uint8_t idx = irq_no_to_idx[irq_no];
|
|
if (idx != IRQ_IDX_MAX) {
|
|
icu_cbs[idx] = func;
|
|
icu_params[idx] = param;
|
|
}
|
|
}
|
|
|
|
static void ra_icu_callback(uint8_t irq_no) {
|
|
uint8_t idx = irq_no_to_idx[irq_no];
|
|
if (idx != IRQ_IDX_MAX) {
|
|
if (bounce_flag[idx]) {
|
|
if ((mtick() - bounce_start[idx]) > bounce_period[idx]) {
|
|
bounce_flag[idx] = false;
|
|
} else {
|
|
return;
|
|
}
|
|
}
|
|
if (icu_cbs[idx] != NULL) {
|
|
if (!bounce_flag[idx]) {
|
|
bounce_start[idx] = mtick();
|
|
bounce_flag[idx] = true;
|
|
(*icu_cbs[idx])(icu_params[idx]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* pin: cpu pin
|
|
* irq_no: IRQ number
|
|
* cond: 0: falling, 1: rising, 2: both edge, 3 low level
|
|
*/
|
|
void ra_icu_trigger_irq_no(uint8_t irq_no, uint32_t cond) {
|
|
icu_reg->IRQCR_b[irq_no].IRQMD = (uint8_t)cond;
|
|
}
|
|
|
|
void ra_icu_trigger_pin(uint32_t pin, uint32_t cond) {
|
|
bool find = false;
|
|
uint8_t irq_no;
|
|
find = ra_icu_find_irq_no(pin, &irq_no);
|
|
if (find) {
|
|
ra_icu_trigger_irq_no(irq_no, cond);
|
|
}
|
|
}
|
|
|
|
void ra_icu_set_bounce(uint8_t irq_no, uint32_t bounce) {
|
|
uint8_t idx = irq_no_to_idx[irq_no];
|
|
if (idx != IRQ_IDX_MAX) {
|
|
bounce_period[idx] = bounce;
|
|
}
|
|
}
|
|
|
|
static void ra_icu_bounce_init(void) {
|
|
uint32_t idx;
|
|
for (idx = 0; idx < IRQ_IDX_MAX; idx++) {
|
|
bounce_flag[idx] = false;
|
|
bounce_period[idx] = DEFAULT_BOUNCE_PERIOD;
|
|
}
|
|
}
|
|
|
|
void ra_icu_init(void) {
|
|
ra_icu_bounce_init();
|
|
}
|
|
|
|
void ra_icu_deinit(void) {
|
|
uint32_t idx;
|
|
for (idx = 0; idx < IRQ_IDX_MAX; idx++) {
|
|
R_BSP_IrqDisable(idx_to_irq_vec[idx]);
|
|
}
|
|
}
|
|
|
|
void ra_icu_swint(uint8_t irq_no) {
|
|
// RA MCU doesn't support STM32 EXTINT SWINT
|
|
// just call callback function
|
|
uint8_t idx = irq_no_to_idx[irq_no];
|
|
if (icu_cbs[idx] != NULL) {
|
|
(*icu_cbs[idx])(icu_params[idx]);
|
|
}
|
|
}
|
|
|
|
__WEAK void r_icu_isr(void) {
|
|
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
|
uint32_t irq_no = (uint32_t)irq_to_ch[(uint32_t)irq];
|
|
R_BSP_IrqStatusClear(irq);
|
|
ra_icu_callback(irq_no);
|
|
}
|