372 lines
18 KiB
C
372 lines
18 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "py/mphal.h"
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#include "samd_soc.h"
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#include "pendsv.h"
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#include "shared/runtime/softtimer.h"
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typedef void (*ISR)(void);
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extern uint32_t _estack, _sidata, _sdata, _edata, _sbss, _ebss;
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extern void Default_Handler(void);
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extern void SysTick_Handler(void);
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extern void PendSV_Handler(void);
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extern void EIC_Handler(void);
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const ISR isr_vector[];
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volatile uint32_t systick_ms;
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volatile uint32_t ticks_us64_upper;
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#if defined(MCU_SAMD21)
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volatile uint32_t rng_state;
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#endif
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void Reset_Handler(void) __attribute__((naked));
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void Reset_Handler(void) {
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// Set stack pointer
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#if __CORTEX_M >= 0x03
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__asm volatile ("ldr sp, =_estack");
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#else
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__asm volatile ("ldr r0, =_estack");
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__asm volatile ("mov sp, r0");
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#endif
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// Copy .data section from flash to RAM
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for (uint32_t *src = &_sidata, *dest = &_sdata; dest < &_edata;) {
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*dest++ = *src++;
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}
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// Zero out .bss section
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for (uint32_t *dest = &_sbss; dest < &_ebss;) {
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*dest++ = 0;
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}
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// When we get here: stack is initialised, bss is clear, data is copied
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#if __FPU_PRESENT == 1 && __FPU_USED == 1
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// Set CP10 and CP11 Full Access
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SCB->CPACR |= (3UL << 10 * 2) | (3UL << 11 * 2);
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#endif
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// SCB->VTOR
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*((volatile uint32_t *)0xe000ed08) = (uint32_t)&isr_vector;
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// SCB->CCR: enable 8-byte stack alignment for IRQ handlers, in accord with EABI
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*((volatile uint32_t *)0xe000ed14) |= 1 << 9;
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// Initialise the cpu and peripherals
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samd_init();
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// Now that we have a basic system up and running we can call main
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samd_main();
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// we must not return
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for (;;) {
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}
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}
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void Default_Handler(void) {
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for (;;) {
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}
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}
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void SysTick_Handler(void) {
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#if defined(MCU_SAMD21)
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// Use the phase jitter between the clocks to get some entropy
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// and accumulate the random number register with a "spiced" LCG.
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rng_state = (rng_state * 32310901 + 1) ^ (REG_TC4_COUNT32_COUNT >> 1);
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#endif
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uint32_t next_tick = systick_ms + 1;
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systick_ms = next_tick;
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if (soft_timer_next == next_tick) {
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pendsv_schedule_dispatch(PENDSV_DISPATCH_SOFT_TIMER, soft_timer_handler);
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}
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}
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void us_timer_IRQ(void) {
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#if defined(MCU_SAMD21)
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if (TC4->COUNT32.INTFLAG.reg & TC_INTFLAG_OVF) {
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ticks_us64_upper++;
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}
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TC4->COUNT32.INTFLAG.reg = TC_INTFLAG_OVF;
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#elif defined(MCU_SAMD51)
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if (TC0->COUNT32.INTFLAG.reg & TC_INTFLAG_OVF) {
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ticks_us64_upper++;
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}
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TC0->COUNT32.INTFLAG.reg = TC_INTFLAG_OVF;
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#endif
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}
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// Sercom IRQ handler support
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void (*sercom_irq_handler_table[SERCOM_INST_NUM])(int num) = {};
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void sercom_register_irq(int sercom_id, void (*sercom_irq_handler)) {
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if (sercom_id < SERCOM_INST_NUM) {
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sercom_irq_handler_table[sercom_id] = sercom_irq_handler;
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}
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}
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static inline void common_sercom_irq_handler(int sercom_id) {
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if (sercom_irq_handler_table[sercom_id]) {
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sercom_irq_handler_table[sercom_id](sercom_id);
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}
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}
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void Sercom0_Handler(void) {
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common_sercom_irq_handler(0);
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}
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void Sercom1_Handler(void) {
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common_sercom_irq_handler(1);
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}
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void Sercom2_Handler(void) {
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common_sercom_irq_handler(2);
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}
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void Sercom3_Handler(void) {
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common_sercom_irq_handler(3);
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}
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void Sercom4_Handler(void) {
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common_sercom_irq_handler(4);
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}
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void Sercom5_Handler(void) {
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common_sercom_irq_handler(5);
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}
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#if defined(MCU_SAMD51)
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void Sercom6_Handler(void) {
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common_sercom_irq_handler(6);
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}
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void Sercom7_Handler(void) {
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common_sercom_irq_handler(7);
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}
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#endif
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#if defined(MCU_SAMD21)
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const ISR isr_vector[] __attribute__((section(".isr_vector"))) = {
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(ISR)&_estack,
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&Reset_Handler,
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&Default_Handler, // NMI_Handler
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&Default_Handler, // HardFault_Handler
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&Default_Handler, // MemManage_Handler
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&Default_Handler, // BusFault_Handler
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&Default_Handler, // UsageFault_Handler
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0,
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0,
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0,
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0,
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&Default_Handler, // SVC_Handler
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&Default_Handler, // DebugMon_Handler
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0,
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&PendSV_Handler, // PendSV_Handler
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&SysTick_Handler, // SysTick_Handler
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0, // 0 Power Manager (PM)
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0, // 1 System Control (SYSCTRL)
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0, // 2 Watchdog Timer (WDT)
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0, // 3 Real-Time Counter (RTC)
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&EIC_Handler, // 4 External Interrupt Controller (EIC)
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0, // 5 Non-Volatile Memory Controller (NVMCTRL)
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0, // 6 Direct Memory Access Controller (DMAC)
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USB_Handler_wrapper,// 7 Universal Serial Bus (USB)
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0, // 8 Event System Interface (EVSYS)
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&Sercom0_Handler, // 9 Serial Communication Interface 0 (SERCOM0)
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&Sercom1_Handler, // 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1)
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&Sercom2_Handler, // 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2)
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&Sercom3_Handler, // 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3)
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&Sercom4_Handler, // 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4)
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&Sercom5_Handler, // 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5)
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0, // 15 Timer Counter Control 0 (TCC0)
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0, // 16 Timer Counter Control 1 (TCC1)
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0, // 17 Timer Counter Control 2 (TCC2)
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0, // 18 Basic Timer Counter 3 (TC3)
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&us_timer_IRQ, // 19 Basic Timer Counter 4 (TC4)
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0, // 20 Basic Timer Counter 5 (TC5)
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0, // 21 Basic Timer Counter 6 (TC6)
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0, // 22 Basic Timer Counter 7 (TC7)
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0, // 23 Analog Digital Converter (ADC)
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0, // 24 Analog Comparators (AC)
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0, // 25 Digital Analog Converter (DAC)
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0, // 26 Peripheral Touch Controller (PTC)
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0, // 27 Inter-IC Sound Interface (I2S)
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};
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#else
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const ISR isr_vector[] __attribute__((section(".isr_vector"))) = {
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(ISR)&_estack,
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&Reset_Handler,
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&Default_Handler, // NMI_Handler
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&Default_Handler, // HardFault_Handler
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&Default_Handler, // MemManage_Handler
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&Default_Handler, // BusFault_Handler
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&Default_Handler, // UsageFault_Handler
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0,
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0,
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0,
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0,
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&Default_Handler, // SVC_Handler
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&Default_Handler, // DebugMon_Handler
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0,
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&PendSV_Handler, // PendSV_Handler
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&SysTick_Handler, // SysTick_Handler
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0, // 0 Power Manager (PM)
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0, // 1 Main Clock (MCLK)
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0, // 2 Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0
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0, // 3 Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1
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0, // 4 Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY
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0, // 5 Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0
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0, // 6 Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1
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0, // 7 32kHz Oscillators Control (OSC32KCTRL)
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0, // 8 Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUP
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0, // 9 Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET
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0, // 10 Watchdog Timer (WDT)
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0, // 11 Real-Time Counter (RTC)
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&EIC_Handler, // 12 External Interrupt Controller (EIC): EIC_EXTINT_0
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&EIC_Handler, // 13 External Interrupt Controller (EIC): EIC_EXTINT_1
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&EIC_Handler, // 14 External Interrupt Controller (EIC): EIC_EXTINT_2
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&EIC_Handler, // 15 External Interrupt Controller (EIC): EIC_EXTINT_3
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&EIC_Handler, // 16 External Interrupt Controller (EIC): EIC_EXTINT_4
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&EIC_Handler, // 17 External Interrupt Controller (EIC): EIC_EXTINT_5
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&EIC_Handler, // 18 External Interrupt Controller (EIC): EIC_EXTINT_6
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&EIC_Handler, // 19 External Interrupt Controller (EIC): EIC_EXTINT_7
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&EIC_Handler, // 20 External Interrupt Controller (EIC): EIC_EXTINT_8
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&EIC_Handler, // 21 External Interrupt Controller (EIC): EIC_EXTINT_9
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&EIC_Handler, // 22 External Interrupt Controller (EIC): EIC_EXTINT_10
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&EIC_Handler, // 23 External Interrupt Controller (EIC): EIC_EXTINT_11
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&EIC_Handler, // 24 External Interrupt Controller (EIC): EIC_EXTINT_12
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&EIC_Handler, // 25 External Interrupt Controller (EIC): EIC_EXTINT_13
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&EIC_Handler, // 26 External Interrupt Controller (EIC): EIC_EXTINT_14
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&EIC_Handler, // 27 External Interrupt Controller (EIC): EIC_EXTINT_15
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0, // 28 Frequency Meter (FREQM)
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0, // 29 Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0 - _7
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0, // 30 Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_8 - _10
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0, // 31 Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0
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0, // 32 Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1
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0, // 33 Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2
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0, // 34 Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3
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0, // 35 Direct Memory Access Controller (DMAC): DMAC_SUSP_4 - _31, DMAC_TCMPL_4 _31, DMAC_TERR_4- _31
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0, // 36 Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0
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0, // 37 Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1
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0, // 38 Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2
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0, // 39 Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3
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0, // 40 Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11
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0, // 41 Peripheral Access Controller (PAC)
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0, // 42 Trigger Allocator (TAL): TAL_BRK
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0, // 43 Trigger Allocator (TAL): TAL_IPS_x
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0,
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0, // 45 RAM ECC (RAMECC)
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&Sercom0_Handler, // 46 Serial Communication Interface 0 (SERCOM0): SERCOM0_0
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&Sercom0_Handler, // 47 Serial Communication Interface 0 (SERCOM0): SERCOM0_1
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&Sercom0_Handler, // 48 Serial Communication Interface 0 (SERCOM0): SERCOM0_2
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&Sercom0_Handler, // 49 Serial Communication Interface 0 (SERCOM0): SERCOM0_3 - 6
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&Sercom1_Handler, // 50 Serial Communication Interface 1 (SERCOM1): SERCOM1_0
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&Sercom1_Handler, // 51 Serial Communication Interface 1 (SERCOM1): SERCOM1_1
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&Sercom1_Handler, // 52 Serial Communication Interface 1 (SERCOM1): SERCOM1_2
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&Sercom1_Handler, // 53 Serial Communication Interface 1 (SERCOM1): SERCOM1_3 - 6
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&Sercom2_Handler, // 54 Serial Communication Interface 2 (SERCOM2): SERCOM2_0
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&Sercom2_Handler, // 55 Serial Communication Interface 2 (SERCOM2): SERCOM2_1
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&Sercom2_Handler, // 56 Serial Communication Interface 2 (SERCOM2): SERCOM2_2
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&Sercom2_Handler, // 57 Serial Communication Interface 2 (SERCOM2): SERCOM2_3 - 6
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&Sercom3_Handler, // 58 Serial Communication Interface 3 (SERCOM3): SERCOM3_0
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&Sercom3_Handler, // 59 Serial Communication Interface 3 (SERCOM3): SERCOM3_1
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&Sercom3_Handler, // 60 Serial Communication Interface 3 (SERCOM3): SERCOM3_2
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&Sercom3_Handler, // 61 Serial Communication Interface 3 (SERCOM3): SERCOM3_3 - 6
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&Sercom4_Handler, // 62 Serial Communication Interface 4 (SERCOM4): SERCOM4_0
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&Sercom4_Handler, // 63 Serial Communication Interface 4 (SERCOM4): SERCOM4_1
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&Sercom4_Handler, // 64 Serial Communication Interface 4 (SERCOM4): SERCOM4_2
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&Sercom4_Handler, // 65 Serial Communication Interface 4 (SERCOM4): SERCOM4_3 - 6
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&Sercom5_Handler, // 66 Serial Communication Interface 5 (SERCOM5): SERCOM5_0
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&Sercom5_Handler, // 67 Serial Communication Interface 5 (SERCOM5): SERCOM5_1
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&Sercom5_Handler, // 68 Serial Communication Interface 5 (SERCOM5): SERCOM5_2
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&Sercom5_Handler, // 69 Serial Communication Interface 5 (SERCOM5): SERCOM5_3 - 6
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&Sercom6_Handler, // 70 Serial Communication Interface 6 (SERCOM6): SERCOM6_0
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&Sercom6_Handler, // 71 Serial Communication Interface 6 (SERCOM6): SERCOM6_1
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&Sercom6_Handler, // 72 Serial Communication Interface 6 (SERCOM6): SERCOM6_2
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&Sercom6_Handler, // 73 Serial Communication Interface 6 (SERCOM6): SERCOM6_3 - 6
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&Sercom7_Handler, // 74 Serial Communication Interface 7 (SERCOM7): SERCOM7_0
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&Sercom7_Handler, // 75 Serial Communication Interface 7 (SERCOM7): SERCOM7_1
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&Sercom7_Handler, // 76 Serial Communication Interface 7 (SERCOM7): SERCOM7_2
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&Sercom7_Handler, // 77 Serial Communication Interface 7 (SERCOM7): SERCOM7_3 - 6
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0, // 78 Control Area Network 0 (CAN0)
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0, // 79 Control Area Network 1 (CAN1)
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&USB_0_Handler_wrapper, // 80 Universal Serial Bus (USB): USB_EORSM_DNRS, ...
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&USB_1_Handler_wrapper, // 81 Universal Serial Bus (USB): USB_SOF_HSOF
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&USB_2_Handler_wrapper, // 82 Universal Serial Bus (USB): USB_TRCPT0_0 - _7
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&USB_3_Handler_wrapper, // 83 Universal Serial Bus (USB): USB_TRCPT1_0 - _7
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0, // 84 Ethernet MAC (GMAC)
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0, // 85 Timer Counter Control 0 (TCC0): TCC0_CNT_A ...
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0, // 86 Timer Counter Control 0 (TCC0): TCC0_MC_0
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0, // 87 Timer Counter Control 0 (TCC0): TCC0_MC_1
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0, // 88 Timer Counter Control 0 (TCC0): TCC0_MC_2
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0, // 89 Timer Counter Control 0 (TCC0): TCC0_MC_3
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0, // 90 Timer Counter Control 0 (TCC0): TCC0_MC_4
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0, // 91 Timer Counter Control 0 (TCC0): TCC0_MC_5
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0, // 92 Timer Counter Control 1 (TCC1): TCC1_CNT_A ...
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0, // 93 Timer Counter Control 1 (TCC1): TCC1_MC_0
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0, // 94 Timer Counter Control 1 (TCC1): TCC1_MC_1
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0, // 95 Timer Counter Control 1 (TCC1): TCC1_MC_2
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0, // 96 Timer Counter Control 1 (TCC1): TCC1_MC_3
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0, // 97 Timer Counter Control 2 (TCC2): TCC2_CNT_A ...
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0, // 98 Timer Counter Control 2 (TCC2): TCC2_MC_0
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0, // 99 Timer Counter Control 2 (TCC2): TCC2_MC_1
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0, // 100 Timer Counter Control 2 (TCC2): TCC2_MC_2
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0, // 101 Timer Counter Control 3 (TCC3): TCC3_CNT_A ...
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0, // 102 Timer Counter Control 3 (TCC3): TCC3_MC_0
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0, // 103 Timer Counter Control 3 (TCC3): TCC3_MC_1
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0, // 104 Timer Counter Control 4 (TCC4): TCC4_CNT_A ...
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0, // 105 Timer Counter Control 4 (TCC4): TCC4_MC_0
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0, // 106 Timer Counter Control 4 (TCC4): TCC4_MC_1
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&us_timer_IRQ, // 107 Basic Timer Counter 0 (TC0)
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0, // 108 Basic Timer Counter 1 (TC1)
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0, // 109 Basic Timer Counter 2 (TC2)
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0, // 110 Basic Timer Counter 3 (TC3)
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0, // 111 Basic Timer Counter 4 (TC4)
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0, // 112 Basic Timer Counter 5 (TC5)
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0, // 113 Basic Timer Counter 6 (TC6)
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0, // 114 Basic Timer Counter 7 (TC7)
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0, // 115 Quadrature Decoder (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A
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0, // 116 Quadrature Decoder (PDEC): PDEC_MC_0
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0, // 117 Quadrature Decoder (PDEC): PDEC_MC_1
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0, // 118 Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON
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0, // 119 Analog Digital Converter 0 (ADC0): ADC0_RESRDY
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0, // 120 Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON
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0, // 121 Analog Digital Converter 1 (ADC1): ADC1_RESRDY
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0, // 122 Analog Comparators (AC)
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0, // 123 Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_x, DAC_UNDERRUN_A_x
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0, // 124 Digital-to-Analog Converter (DAC): DAC_EMPTY_0
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0, // 125 Digital-to-Analog Converter (DAC): DAC_EMPTY_1
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0, // 126 Digital-to-Analog Converter (DAC): DAC_RESRDY_0
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0, // 127 Digital-to-Analog Converter (DAC): DAC_RESRDY_1
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0, // 128 Inter-IC Sound Interface (I2S)
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0, // 129 Parallel Capture Controller (PCC)
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0, // 130 Advanced Encryption Standard (AES)
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0, // 131 True Random Generator (TRNG)
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0, // 132 Integrity Check Monitor (ICM)
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0, // 133 PUblic-Key Cryptography Controller (PUKCC)
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0, // 134 Quad SPI interface (QSPI)
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0, // 135 SD/MMC Host Controller 0 (SDHC0)
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0, // 136 SD/MMC Host Controller 1 (SDHC1)
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};
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#endif
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