47550ef2cd
MCUs that have a PLLSAI can use it to generate a 48MHz clock for USB, SDIO and RNG peripherals. In such cases the SYSCLK is not restricted to values that allow the system PLL to generate 48MHz, but can be any frequency. This patch allows such configurability for F7 MCUs, allowing the SYSCLK to be set in 2MHz increments via machine.freq(). PLLSAI will only be enabled if needed, and consumes about 1mA extra. This fine grained control of frequency is useful to get accurate SPI baudrates, for example. |
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bare-arm | ||
cc3200 | ||
esp32 | ||
esp8266 | ||
minimal | ||
nrf | ||
pic16bit | ||
qemu-arm | ||
stm32 | ||
teensy | ||
unix | ||
windows | ||
zephyr |