589 lines
26 KiB
C
589 lines
26 KiB
C
/**
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******************************************************************************
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* @file stm32l4xx_hal_dma.h
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* @author MCD Application Team
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* @version V1.3.0
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* @date 29-January-2016
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* @brief Header file of DMA HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32L4xx_HAL_DMA_H
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#define __STM32L4xx_HAL_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l4xx_hal_def.h"
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/** @addtogroup STM32L4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup DMA_Exported_Types DMA Exported Types
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* @{
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*/
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/**
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* @brief DMA Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Request; /*!< Specifies the request selected for the specified channel.
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This parameter can be a value of @ref DMA_request */
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uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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from memory to memory or from peripheral to memory.
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This parameter can be a value of @ref DMA_Data_transfer_direction */
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uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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This parameter can be a value of @ref DMA_Memory_incremented_mode */
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uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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This parameter can be a value of @ref DMA_Peripheral_data_size */
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uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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This parameter can be a value of @ref DMA_Memory_data_size */
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uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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This parameter can be a value of @ref DMA_mode
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@note The circular buffer mode cannot be used if the memory-to-memory
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data transfer is configured on the selected Channel */
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uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
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This parameter can be a value of @ref DMA_Priority_level */
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} DMA_InitTypeDef;
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/**
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* @brief DMA Configuration enumeration values definition
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*/
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typedef enum
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{
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DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
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DMA_PRIORITY = 1 /*!< Control related priority level Parameter in DMA_InitTypeDef */
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} DMA_ControlTypeDef;
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/**
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* @brief HAL DMA State structures definition
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*/
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typedef enum
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{
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HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
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HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
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HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
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HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
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HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
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HAL_DMA_STATE_ERROR = 0x04 /*!< DMA error state */
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}HAL_DMA_StateTypeDef;
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/**
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* @brief HAL DMA Error Code structure definition
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*/
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typedef enum
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{
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HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
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HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
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}HAL_DMA_LevelCompleteTypeDef;
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/**
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* @brief DMA handle Structure definition
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*/
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typedef struct __DMA_HandleTypeDef
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{
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DMA_Channel_TypeDef *Instance; /*!< Register base address */
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DMA_InitTypeDef Init; /*!< DMA communication parameters */
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HAL_LockTypeDef Lock; /*!< DMA locking object */
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__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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void *Parent; /*!< Parent object state */
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void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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__IO uint32_t ErrorCode; /*!< DMA Error code */
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}DMA_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants DMA Exported Constants
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* @{
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*/
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/** @defgroup DMA_Error_Code DMA Error Code
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* @{
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*/
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#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
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#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
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#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
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/**
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* @}
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*/
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/** @defgroup DMA_request DMA request
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* @{
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*/
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#define DMA_REQUEST_0 ((uint32_t)0x00000000)
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#define DMA_REQUEST_1 ((uint32_t)0x00000001)
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#define DMA_REQUEST_2 ((uint32_t)0x00000002)
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#define DMA_REQUEST_3 ((uint32_t)0x00000003)
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#define DMA_REQUEST_4 ((uint32_t)0x00000004)
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#define DMA_REQUEST_5 ((uint32_t)0x00000005)
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#define DMA_REQUEST_6 ((uint32_t)0x00000006)
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#define DMA_REQUEST_7 ((uint32_t)0x00000007)
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/**
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* @}
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*/
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/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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* @{
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*/
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#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
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#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
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#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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* @{
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*/
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#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
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#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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* @{
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*/
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#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
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#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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* @{
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*/
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#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
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#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
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#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_data_size DMA Memory data size
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* @{
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*/
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#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
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#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
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#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
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/**
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* @}
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*/
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/** @defgroup DMA_mode DMA mode
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* @{
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*/
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#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
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#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
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/**
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* @}
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*/
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/** @defgroup DMA_Priority_level DMA Priority level
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* @{
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*/
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#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
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#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
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#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
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#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
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/**
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* @}
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*/
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/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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* @{
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*/
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#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
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#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
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#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
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/**
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* @}
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*/
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/** @defgroup DMA_flag_definitions DMA flag definitions
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* @{
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*/
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#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
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#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
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#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
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#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
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#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
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#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
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#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
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#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
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#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
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#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
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#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
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#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
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#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
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#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
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#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
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#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
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#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
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#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
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#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
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#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
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#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
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#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
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#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
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#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
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#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
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#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
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#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
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#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros -----------------------------------------------------------*/
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/** @defgroup DMA_Exported_Macros DMA Exported Macros
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* @{
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*/
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/** @brief Reset DMA handle state.
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* @param __HANDLE__: DMA handle
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* @retval None
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*/
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#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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/**
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* @brief Enable the specified DMA Channel.
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* @param __HANDLE__: DMA handle
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* @retval None
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*/
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#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
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/**
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* @brief Disable the specified DMA Channel.
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* @param __HANDLE__: DMA handle
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* @retval None
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*/
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#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
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/* Interrupt & Flag management */
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/**
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* @brief Return the current DMA Channel transfer complete flag.
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* @param __HANDLE__: DMA handle
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* @retval The specified transfer complete flag index.
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*/
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#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
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(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
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DMA_FLAG_TC7)
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/**
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* @brief Return the current DMA Channel half transfer complete flag.
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* @param __HANDLE__: DMA handle
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* @retval The specified half transfer complete flag index.
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*/
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#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
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(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
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DMA_FLAG_HT7)
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/**
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* @brief Return the current DMA Channel transfer error flag.
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* @param __HANDLE__: DMA handle
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* @retval The specified transfer error flag index.
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*/
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#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
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(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
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DMA_FLAG_TE7)
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/**
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* @brief Return the current DMA Channel Global interrupt flag.
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* @param __HANDLE__: DMA handle
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* @retval The specified transfer error flag index.
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*/
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#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
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(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
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((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
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DMA_ISR_GIF7)
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/**
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* @brief Get the DMA Channel pending flags.
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* @param __HANDLE__: DMA handle
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* @param __FLAG__: Get the specified flag.
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* This parameter can be any combination of the following values:
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* @arg DMA_FLAG_TCIFx: Transfer complete flag
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* @arg DMA_FLAG_HTIFx: Half transfer complete flag
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* @arg DMA_FLAG_TEIFx: Transfer error flag
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* @arg DMA_ISR_GIFx: Global interrupt flag
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* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
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* @retval The state of FLAG (SET or RESET).
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*/
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#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
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(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
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/**
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* @brief Clear the DMA Channel pending flags.
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* @param __HANDLE__: DMA handle
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* @param __FLAG__: specifies the flag to clear.
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* This parameter can be any combination of the following values:
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* @arg DMA_FLAG_TCIFx: Transfer complete flag
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* @arg DMA_FLAG_HTIFx: Half transfer complete flag
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* @arg DMA_FLAG_TEIFx: Transfer error flag
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* @arg DMA_ISR_GIFx: Global interrupt flag
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* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
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* @retval None
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*/
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#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
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(DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
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/**
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* @brief Enable the specified DMA Channel interrupts.
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* @param __HANDLE__: DMA handle
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* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
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* This parameter can be any combination of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
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* @arg DMA_IT_HT: Half transfer complete interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @retval None
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*/
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#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
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/**
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* @brief Disable the specified DMA Channel interrupts.
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* @param __HANDLE__: DMA handle
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* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
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* This parameter can be any combination of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
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* @arg DMA_IT_HT: Half transfer complete interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @retval None
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*/
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#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
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/**
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* @brief Check whether the specified DMA Channel interrupt is enabled or not.
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* @param __HANDLE__: DMA handle
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* @param __INTERRUPT__: specifies the DMA interrupt source to check.
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* This parameter can be one of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @retval The state of DMA_IT (SET or RESET).
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*/
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#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
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|
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/**
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* @}
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*/
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|
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup DMA_Exported_Functions
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* @{
|
|
*/
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|
|
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/** @addtogroup DMA_Exported_Functions_Group1
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* @{
|
|
*/
|
|
/* Initialization and de-initialization functions *****************************/
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
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|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup DMA_Exported_Functions_Group2
|
|
* @{
|
|
*/
|
|
/* IO operation functions *****************************************************/
|
|
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup DMA_Exported_Functions_Group3
|
|
* @{
|
|
*/
|
|
/* Peripheral State and Error functions ***************************************/
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private macros ------------------------------------------------------------*/
|
|
/** @defgroup DMA_Private_Macros DMA Private Macros
|
|
* @{
|
|
*/
|
|
|
|
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
|
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
|
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
|
|
|
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
|
|
|
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
|
((STATE) == DMA_PINC_DISABLE))
|
|
|
|
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
|
((STATE) == DMA_MINC_DISABLE))
|
|
|
|
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
|
|
((REQUEST) == DMA_REQUEST_1) || \
|
|
((REQUEST) == DMA_REQUEST_2) || \
|
|
((REQUEST) == DMA_REQUEST_3) || \
|
|
((REQUEST) == DMA_REQUEST_4) || \
|
|
((REQUEST) == DMA_REQUEST_5) || \
|
|
((REQUEST) == DMA_REQUEST_6) || \
|
|
((REQUEST) == DMA_REQUEST_7))
|
|
|
|
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
|
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
|
((SIZE) == DMA_PDATAALIGN_WORD))
|
|
|
|
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
|
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
|
((SIZE) == DMA_MDATAALIGN_WORD ))
|
|
|
|
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
|
((MODE) == DMA_CIRCULAR))
|
|
|
|
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
|
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
|
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
|
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32L4xx_HAL_DMA_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|