249 lines
7.8 KiB
C
249 lines
7.8 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_clock.h"
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#include "flexspi_hyper_flash.h"
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// Copy of a few (pseudo-)functions from fsl_clock.h, which were nor reliably
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// inlined when they should be. That caused DEBUG mode to fail.
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// It does not increase the code size, since they were supposed to be inline.
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__attribute__((always_inline)) static inline void clock_set_div(clock_div_t divider, uint32_t value) {
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uint32_t busyShift;
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busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
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CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
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(((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
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/* Clock switch need Handshake? */
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if (CCM_NO_BUSY_WAIT != busyShift) {
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/* Wait until CCM internal handshake finish. */
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while (CCM->CDHIPR & (1U << busyShift)) {
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}
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}
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}
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__attribute__((always_inline)) static inline void clock_control_gate(clock_ip_name_t name, clock_gate_value_t value) {
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uint32_t index = ((uint32_t)name) >> 8U;
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uint32_t shift = ((uint32_t)name) & 0x1FU;
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volatile uint32_t *reg;
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reg = ((volatile uint32_t *)&CCM->CCGR0) + index;
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*reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift);
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}
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__attribute__((always_inline)) static inline void clock_enable_clock(clock_ip_name_t name) {
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clock_control_gate(name, kCLOCK_ClockNeededRunWait);
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}
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__attribute__((always_inline)) static inline void clock_disable_clock(clock_ip_name_t name) {
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clock_control_gate(name, kCLOCK_ClockNotNeeded);
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}
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#define DIV_PAGE_PGM 4
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#define DIV_ERASE_PGM 4
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#define DIV_READ 0
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static void SetFlexSPIDiv(uint32_t div) __attribute__((section(".ram_functions")));
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static void SetFlexSPIDiv(uint32_t div) {
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FLEXSPI_Enable(FLEXSPI, false);
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clock_disable_clock(kCLOCK_FlexSpi);
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clock_set_div(kCLOCK_FlexspiDiv, div); /* flexspi clock 332M, DDR mode, internal clock 166M. */
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clock_enable_clock(kCLOCK_FlexSpi);
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FLEXSPI_Enable(FLEXSPI, true);
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}
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status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) {
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flexspi_transfer_t flashXfer;
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status_t status;
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flashXfer.deviceAddress = addr * 2;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA;
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flashXfer.data = buffer;
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flashXfer.dataSize = bytes;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) {
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flexspi_transfer_t flashXfer;
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status_t status;
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flashXfer.deviceAddress = addr * 2;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA;
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flashXfer.data = buffer;
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flashXfer.dataSize = bytes;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) {
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flexspi_transfer_t flashXfer;
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status_t status;
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/* Write enable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) {
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/* Wait status ready. */
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bool isBusy;
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uint32_t readValue;
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status_t status;
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flexspi_transfer_t flashXfer;
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 2;
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do {
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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if (readValue & 0x8000) {
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isBusy = false;
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} else {
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isBusy = true;
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}
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if (readValue & 0x3200) {
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status = kStatus_Fail;
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break;
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}
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} while (isBusy);
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return status;
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}
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status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) {
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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status = flexspi_nor_write_enable(base, address);
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if (status != kStatus_Success) {
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return status;
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}
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 4;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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return status;
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}
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status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src, uint32_t size) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src, uint32_t size) {
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Speed down flexspi clock */
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SetFlexSPIDiv(DIV_PAGE_PGM);
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/* Write enable */
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status = flexspi_nor_write_enable(base, address);
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if (status != kStatus_Success) {
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return status;
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}
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/* Prepare page program command */
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
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flashXfer.data = (uint32_t *)src;
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flashXfer.dataSize = size;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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SetFlexSPIDiv(DIV_READ);
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return status;
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}
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status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base) {
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/*
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* Read ID-CFI Parameters
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*/
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// CFI Entry
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status_t status;
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uint32_t buffer[2];
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uint8_t data[4] = {0x00, 0x98};
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status = flexspi_nor_hyperbus_write(base, 0x555, (uint32_t *)data, 2);
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if (status != kStatus_Success) {
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return status;
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}
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// ID-CFI Read
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// Read Query Unique ASCII String
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status = flexspi_nor_hyperbus_read(base, 0x10, &buffer[0], sizeof(buffer));
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if (status != kStatus_Success) {
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return status;
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}
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buffer[1] &= 0xFFFF;
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// Check that the data read out is unicode "QRY" in big-endian order
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if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900)) {
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status = kStatus_Fail;
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return status;
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}
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// ASO Exit 0xF000
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data[1] = 0xF0;
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status = flexspi_nor_hyperbus_write(base, 0x0, (uint32_t *)data, 2);
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if (status != kStatus_Success) {
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return status;
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}
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return status;
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}
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