250 lines
7.7 KiB
C
250 lines
7.7 KiB
C
/*
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* Based largely on examples provided by NXP:
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*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Port-specific extensions and adaptions:
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*
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* The MIT License (MIT)
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* Copyright (c) 2021 Damien P. George
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* Copyright (c) 2021 Philipp Ebensberger
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <assert.h>
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#include "fsl_common.h"
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#include "flexspi_nor_flash.h"
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void flexspi_nor_reset(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));
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void flexspi_nor_reset(FLEXSPI_Type *base) {
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// Using content of FLEXSPI_SoftwareReset directly to prevent issues when compiler does not inline function
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base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
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while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) {
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}
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}
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status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) {
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flexspi_transfer_t flashXfer;
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status_t status;
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/* Write neable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) {
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/* Wait status ready. */
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bool isBusy;
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uint32_t readValue;
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status_t status;
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flexspi_transfer_t flashXfer;
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 1;
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do {
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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if (FLASH_BUSY_STATUS_POL) {
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if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
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isBusy = false;
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} else {
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isBusy = true;
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}
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} else {
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if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) {
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isBusy = true;
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} else {
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isBusy = false;
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}
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}
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} while (isBusy);
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return status;
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}
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status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base) {
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flexspi_transfer_t flashXfer;
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status_t status;
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uint32_t writeValue = 0x40;
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/* Write neable */
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status = flexspi_nor_write_enable(base, 0);
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if (status != kStatus_Success) {
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return status;
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}
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/* Enable quad mode. */
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
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flashXfer.data = &writeValue;
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flashXfer.dataSize = 1;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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return status;
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}
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status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) {
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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status = flexspi_nor_write_enable(base, address);
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if (status != kStatus_Success) {
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return status;
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}
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/* Erase sector */
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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flexspi_nor_reset(base);
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return status;
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}
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status_t flexspi_nor_flash_erase_block(FLEXSPI_Type *base, uint32_t address) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_flash_erase_block(FLEXSPI_Type *base, uint32_t address) {
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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status = flexspi_nor_write_enable(base, address);
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if (status != kStatus_Success) {
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return status;
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}
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/* Erase sector */
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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flexspi_nor_reset(base);
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return status;
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}
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status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src, uint32_t size) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src, uint32_t size) {
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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status = flexspi_nor_write_enable(base, dstAddr);
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if (status != kStatus_Success) {
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return status;
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}
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/* Prepare page program command */
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flashXfer.deviceAddress = dstAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
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flashXfer.data = (uint32_t *)src;
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flashXfer.dataSize = size;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success) {
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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flexspi_nor_reset(BOARD_FLEX_SPI);
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return status;
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}
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status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId) __attribute__((section(".ram_functions")));
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status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId) {
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uint32_t temp;
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flexspi_transfer_t flashXfer;
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID;
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flashXfer.data = &temp;
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flashXfer.dataSize = 2;
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status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
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*vendorId = temp;
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return status;
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}
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