223 lines
7.6 KiB
C
223 lines
7.6 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Philipp Ebensberger
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "pin.h"
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void pin_init(void) {
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return;
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}
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uint32_t pin_get_mode(const machine_pin_obj_t *pin) {
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uint32_t pin_mode = PIN_MODE_ALT;
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uint32_t config_register = *((volatile uint32_t *)pin->configRegister);
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uint8_t af_mode = pin_get_af(pin);
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if (af_mode == PIN_AF_MODE_ALT5) {
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bool open_drain_enabled = (config_register & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) >> IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT;
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if (open_drain_enabled) {
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pin_mode = PIN_MODE_OPEN_DRAIN;
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} else {
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// Check pin direction
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if ((pin->gpio->GDIR & (1U << pin->pin)) >> pin->pin) {
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pin_mode = PIN_MODE_OUT;
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} else {
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pin_mode = PIN_MODE_IN;
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}
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}
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}
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return pin_mode;
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}
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uint32_t pin_get_af(const machine_pin_obj_t *pin) {
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uint32_t mux_register = *((volatile uint32_t *)pin->muxRegister);
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// Read configured AF-Mode of pin
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return (uint32_t)(mux_register & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) >> IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT;
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}
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uint32_t pin_generate_config(const uint32_t pull, const uint32_t mode, const uint32_t drive, uint32_t config_register) {
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uint32_t pad_config = 0x0UL;
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#if defined MIMXRT117x_SERIES
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// Set Pull-up
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if ((config_register >= 0x400E8350 && config_register <= 0x400E83dc) || // GPIO_AD_xx
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(config_register >= 0x40C08040 && config_register <= 0x40C0807C)) { // GPIO_LPSR_xx
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_SRE(0U); // Set slew rate; there is a discrepancy between doc and header file
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if (pull != PIN_PULL_DISABLED) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PUE(1) | // Pull Enabled
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IOMUXC_SW_PAD_CTL_PAD_PUS(pull != PIN_PULL_DOWN_100K); // Up or DOWn
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}
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} else { // GPIO_SD_Bx_xx
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if (pull == PIN_PULL_DISABLED) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PULL(0b11);
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} else if (pull == PIN_PULL_DOWN_100K) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PULL(0b10);
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} else {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PULL(0b01);
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}
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}
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// Set open Drain; different for LPSR GPIO!
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if (config_register >= 0x40C08040 && config_register <= 0x40C0807C) { // GPIO_LPSR_xx
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if (mode == PIN_MODE_OPEN_DRAIN) {
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pad_config |= 1 << 5; // Open Drain Enabled, no Macro provided
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}
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} else {
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if (mode == PIN_MODE_OPEN_DRAIN) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b1); // Open Drain Enabled
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}
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}
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// Set drive strength
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if (mode != PIN_MODE_IN) {
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if (!IS_GPIO_DRIVE(drive)) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid drive strength: %d"), drive);
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}
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(drive >= PIN_DRIVE_4);
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}
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#else
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_SRE(0U); // Slow Slew Rate
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_SPEED(0b01); // medium(100MHz)
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if (mode == PIN_MODE_OPEN_DRAIN) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b1); // Open Drain Enabled
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} else {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b0); // Open Drain Disabled
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}
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if (pull == PIN_PULL_DISABLED) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(0); // Pull/Keeper Disabled
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} else if (pull == PIN_PULL_HOLD) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | // Pull/Keeper Enabled
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IOMUXC_SW_PAD_CTL_PAD_PUE(0); // Keeper selected
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} else {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | // Pull/Keeper Enabled
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) | // Pull selected
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IOMUXC_SW_PAD_CTL_PAD_PUS(pull);
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}
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if (mode == PIN_MODE_IN) {
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(0b000) | // output driver disabled
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IOMUXC_SW_PAD_CTL_PAD_HYS(1U); // Hysteresis enabled
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} else {
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if (!IS_GPIO_DRIVE(drive)) {
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid drive strength: %d"), drive);
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}
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pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(drive) |
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IOMUXC_SW_PAD_CTL_PAD_HYS(0U); // Hysteresis disabled
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}
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#endif
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return pad_config;
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}
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const machine_pin_obj_t *pin_find(mp_obj_t user_obj) {
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const machine_pin_obj_t *pin_obj;
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// If a pin was provided, then use it
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if (mp_obj_is_type(user_obj, &machine_pin_type)) {
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pin_obj = user_obj;
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return pin_obj;
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}
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// If pin is SMALL_INT
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if (mp_obj_is_small_int(user_obj)) {
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uint8_t value = MP_OBJ_SMALL_INT_VALUE(user_obj);
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if (value < num_board_pins) {
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return machine_pin_board_pins[value];
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}
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}
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// See if the pin name matches a board pin
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pin_obj = pin_find_named_pin(&machine_pin_board_pins_locals_dict, user_obj);
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if (pin_obj) {
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return pin_obj;
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}
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// See if the pin name matches a cpu pin
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pin_obj = pin_find_named_pin(&machine_pin_cpu_pins_locals_dict, user_obj);
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if (pin_obj) {
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return pin_obj;
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}
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mp_raise_ValueError(MP_ERROR_TEXT("Pin doesn't exist"));
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}
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const machine_pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) {
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mp_map_t *named_map = mp_obj_dict_get_map((mp_obj_t)named_pins);
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mp_map_elem_t *named_elem = mp_map_lookup(named_map, name, MP_MAP_LOOKUP);
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if (named_elem != NULL && named_elem->value != NULL) {
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return named_elem->value;
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}
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return NULL;
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}
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const machine_pin_af_obj_t *pin_find_af(const machine_pin_obj_t *pin, uint8_t fn) {
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const machine_pin_af_obj_t *af_obj = NULL;
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for (int i = 0; i < pin->af_list_len; ++i) {
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af_obj = &pin->af_list[i];
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if (af_obj->af_mode == fn) {
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return af_obj;
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}
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}
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return NULL;
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}
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const machine_pin_af_obj_t *pin_find_af_by_base(const machine_pin_obj_t *pin, void *base_ptr[], size_t base_size) {
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const machine_pin_af_obj_t *af_obj = NULL;
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for (int i = 0; i < pin->af_list_len; ++i) {
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af_obj = &pin->af_list[i];
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for (int j = 0; j < base_size; ++j) {
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if (af_obj->instance == base_ptr[j]) {
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return af_obj;
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}
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}
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}
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return NULL;
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}
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const machine_pin_af_obj_t *pin_find_af_by_index(const machine_pin_obj_t *pin, mp_uint_t af_idx) {
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// TODO: Implement pin_find_af_by_index function
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return NULL;
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}
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const machine_pin_af_obj_t *pin_find_af_by_name(const machine_pin_obj_t *pin, const char *name) {
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// TODO: Implement pin_find_af_by_name function
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return NULL;
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}
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